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The “20nm dilemma” was a scaling trade-off: planar CMOS still offered a familiar manufacturing route and attractive density, but its short channels were becoming harder to control without worsening leakage and power. TSMC brought planar 20nm logic to production, then used FinFET transistors at 16nm to address that electrostatic limit.
What “20nm” meant in this case
For TSMC, 20nm was the name of a logic process platform for system-on-chip (SoC) products—not a promise that every transistor feature measured exactly 20 nanometers. TSMC described its platform as planar CMOS, using enhanced high-k metal gate, strained silicon, and copper interconnects with ultra-low-k dielectric material.
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In 2010, TSMC said it would skip 22nm and move directly to this planar 20nm process. The company argued that 20nm offered a better gate-density and performance-to-cost ratio than its 22nm alternative. That was TSMC’s rationale for its own process roadmap, not a rule that every chipmaker had to follow.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Node names are not directly comparable across companies or product types. For example, Samsung’s history uses 20nm-class language for NAND flash memory, while TSMC used 20nm for a logic SoC process. To compare two chips or processes meaningfully, identify the foundry, product type, and transistor architecture instead of relying on the node label alone.
Why planar scaling became difficult
The gate had less control over a shorter channel
A planar transistor’s gate controls whether current can flow through a channel. As the channel gets shorter, the gate has less influence over the whole channel, making it harder to keep the transistor reliably off. TSMC identifies this loss of electrostatic control at short gate lengths as a fundamental limitation of planar scaling.
Leakage and power became harder to manage
Weaker control contributes to leakage and makes it more difficult to meet voltage and power targets as transistors shrink. The dilemma was not simply that planar 20nm could not be manufactured: TSMC advanced it to volume production. Rather, continuing to scale planar transistors created increasingly difficult trade-offs between density, performance, and power.
How FinFET changed the trade-off
A FinFET raises the transistor channel into a fin, allowing the gate to control it from multiple sides rather than only from above. That geometry improves electrostatic control of a short channel and can support lower operating voltage than a comparable planar structure. TSMC says FinFET resolved the poor channel control that had become a fundamental limit for planar devices.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsTSMC’s 2018 technology overview compared its 16FF+ process with planar 20nm: it reported that 16FF+ was 40% faster at the same power, or used 50% less power at the same speed. These are TSMC’s process-level comparisons; they are not a guarantee that every 16FF+ chip will outperform every planar 20nm chip by those amounts. Chip design and operating conditions matter.
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How TSMC’s 20nm and 16nm transitions unfolded
| Milestone | Process and status |
|---|---|
| 2010 | TSMC announced a move directly to planar 20nm, skipping 22nm. |
| 2012 | TSMC’s annual-report material described high-performance 20nm as entering risk-production planning, with volume production scheduled for the first quarter of 2013. |
| 2013 | TSMC reported 20nm qualification for volume manufacture; its 16nm FinFET technology entered risk production. |
| 2015 | TSMC reported 20nm SoC in volume production with stable yield. 16FF+ began volume production in mid-2015. |
These milestones distinguish development and manufacturing stages: an announcement, risk production, qualification for volume manufacture, and actual volume production are not interchangeable. The timeline also shows that TSMC did not simply abandon 20nm when it began developing 16nm FinFET.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Was 20nm a bad node?
Calling 20nm a “bad node” oversimplifies the trade-off. TSMC qualified its planar 20nm process for volume manufacture and later reported its 20nm SoC process in volume production with stable yield. But its own comparison showed why the next architecture was attractive: 16FF+ offered substantial speed or power advantages over planar 20nm under the stated comparison conditions.
So the dilemma was about what should come next. Planar 20nm remained a manufacturable option, while the electrostatic limits of shrinking planar channels made a three-dimensional transistor architecture a compelling route to continued scaling.
Quick Recap
How to compare processes without being misled by the node
- Check the architecture: TSMC’s 20nm logic process was planar; its 16nm technology used FinFETs.
- Ask what is being compared: distinguish a logic SoC process from a memory process, and identify the foundry.
- Read performance claims with their conditions: TSMC’s 16FF+ figures compare speed at equal power or power at equal speed; they are not universal chip benchmarks.
- Separate process maturity stages: announcement, risk production, qualification, and volume production describe different points in a manufacturing roadmap.
- Treat the node name as a platform label: it does not, by itself, specify one physical transistor dimension or prove that one foundry’s process is better than another’s.
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