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For an edge AI device with limited RAM and one coordinated release lifecycle, a single Rust process can be a better starting point than microservices—provided its internal boundaries are treated as seriously as service boundaries. The architecture recorded in paiOS ADR-004 is a modular monolith: paiEngine is one executable assembled from Rust domain crates, with hardware and protocol integrations hidden behind adapters. The stated rationale is lower process and inter-process-communication overhead, shared resource management, faster startup, and a simpler lifecycle on embedded hardware. Those are design goals, not published benchmark results. The same choice reduces failure isolation and independent restartability, so it should be made against explicit recovery, security, scaling, and deployment requirements.
What architecture did the team choose instead of microservices?
The recorded design is a modular monolith: one operating-system process and one executable, but several strongly separated domains inside the Rust codebase. paiOS ADR-004 describes paiEngine as a Cargo workspace made from domain crates rather than a collection of networked services. The available record is the evidence for the implementation; it does not independently establish that paiOS is the platform referred to by every first-person phrase in the headline.
The domains named in the ADR are core, vision, audio, inference, API, and peripherals. Each domain exposes interfaces through modules and Rust traits. A composition root wires concrete implementations together at startup. The result is a single deployment unit whose internal components can still be replaced or tested through ports and adapters.
- One process: the domains share an address space and a lifecycle.
- Explicit boundaries: domain code calls ports, not hardware SDKs or protocol clients directly.
- Replaceable integrations: adapters implement those ports for a particular SoC, device, or external protocol.
- Controlled assembly: the composition root selects implementations and constructs the running system.
This is not an unstructured application in which every module can reach every other module. It is a single deployment artifact with architecture enforced in code rather than by separate process boundaries.
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Why can a single process make sense for an embedded edge-AI device?
The ADR’s argument is operational: when all components run on one constrained device and are released together, multiple service processes can add machinery without delivering an independent deployment benefit. Fewer processes can mean less process-management work and less internal IPC, while a shared address space permits common resource and memory management. The record also identifies faster startup and a simpler lifecycle as goals.
These points are qualitative rationale, not measurements. No comparative figures for RAM consumption, latency, startup time, throughput, reliability, or cost were found for paiEngine. A team should therefore describe the choice as an engineering hypothesis to validate on its target board, not as a proven performance advantage.
Reduced runtime and IPC machinery
A microservice split normally requires each service to be started, supervised, configured, observed, and connected to the others. Internal calls cross an IPC mechanism and require serialization, buffering, and error handling. In a single process, a call between domains can remain an in-process interface call. That removes a class of deployment and communication mechanisms, although it does not remove the need for timeouts, back-pressure, validation, or failure handling.
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Vision, audio, inference, and peripherals may contend for the same memory, accelerators, device handles, and power budget. A single process gives the design one place to coordinate those resources. The ADR treats this shared management as useful on limited-RAM hardware; it does not quantify how much memory or CPU is saved.
One startup and release lifecycle
If the device receives one firmware or application release, one executable can simplify versioning and rollout. The composition root can initialize adapters and domains in a known order, and the supervisor has one primary process to launch. That simplicity is valuable only when components genuinely share a release cadence; teams that need independent rollout lose that benefit.
How does the Rust modularity work inside one executable?
The architecture depends on boundaries that are visible in the type system and module graph. A domain owns its business rules and depends on a port (usually a trait) describing what it needs. An adapter supplies the concrete implementation for a hardware device, protocol, or backend. The composition root chooses the adapter and injects it when the application starts.
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Keep domain code independent of hardware
Inference orchestration should not know the details of a Rockchip SDK. Audio logic should not contain a particular microphone driver’s protocol. Instead, those domains call stable traits, while adapters translate between the trait and the external API. This keeps hardware-specific code localized and makes a second backend possible without rewriting the domain.
Make the composition root the wiring boundary
Constructors, configuration, feature selection, and adapter registration belong in one controlled assembly area. If every module can instantiate its own hardware client, the process may remain single but the architecture becomes difficult to reason about and replace. Central wiring also makes startup failures explicit: a missing device or incompatible backend can be reported before serving requests.
Use crate and module visibility as enforcement
Rust’s visibility rules can prevent accidental access to implementation details. Keep adapter internals private, expose only the port and domain operations needed by callers, and make cross-domain dependencies deliberate. The single process does not provide automatic isolation, so compile-time boundaries and code review carry more of the architectural load.
The trade-off is maintenance. More ports, adapters, and backend choices create more code to own. The ADR acknowledges that abstractions can add complexity even when their runtime cost is small. A boundary should therefore correspond to a real change point—hardware, protocol, storage, or execution policy—not be added merely for ceremony.
How should asynchronous I/O and blocking inference share a Rust process?
The ADR separates asynchronous I/O from blocking computation. Tokio tasks handle I/O-bound work. Long-lived or CPU-bound blocking operations run on dedicated operating-system threads, while short blocking operations use spawn_blocking. The reason is scheduling: if inference blocks the async event loop, server and control work can be starved.
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- Isolate long-running blocking work. Give persistent or expensive operations dedicated OS threads rather than allowing them to occupy the async worker pool indefinitely.
- Use
spawn_blockingfor short, bounded calls. This lets Tokio move a brief blocking operation away from its core async workers, but it is not a substitute for designing limits around unbounded inference. - Control queues and cancellation. Bound requests entering inference, define what happens when work is cancelled, and expose overload errors instead of allowing an unbounded backlog to consume memory.
- Measure on the target device. The ADR gives the scheduling design, not latency or throughput results. Validate event-loop responsiveness, accelerator utilization, and memory behavior on the actual hardware.
This arrangement preserves one process while creating execution boundaries inside it. It is not equivalent to process isolation: a panic, native-library fault, or unrecoverable resource condition can still terminate the whole executable.
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How is inference divided across the device’s accelerators?
The documented plan is hybrid rather than accelerator-exclusive. The NPU handles the principal large-language-model workload. The CPU handles speech-to-text, voice-activity detection, wake-word processing, and vector search. The GPU handles small auxiliary logic models.
| Workload | Assigned resource in the ADR | Architectural implication |
|---|---|---|
| Main LLM workload | NPU | Keep the accelerator integration behind an inference adapter. |
| Speech-to-text | CPU | Schedule as blocking or CPU-bound work rather than on async workers. |
| Voice activity detection | CPU | Coordinate with audio capture and bounded processing queues. |
| Wake-word processing | CPU | Keep the audio path responsive while other inference runs. |
| Vector search | CPU | Account for memory and CPU contention with serving and audio tasks. |
| Small auxiliary logic models | GPU | Represent the GPU backend as a replaceable adapter. |
Rockchip RK3588 is named as the first supported system-on-chip. The record does not identify a board SKU, RAM configuration, peripheral set, or verified retail product. It therefore supports discussing RK3588 as a target SoC, not recommending a particular development board or claiming that every RK3588 board is compatible.
What are the real trade-offs against microservices?
A single process optimizes for a unified device lifecycle; microservices optimize for separation. The following comparison is qualitative because the available architecture record contains no platform benchmark.
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| Decision axis | Single-process modular monolith | Multiple processes or services |
|---|---|---|
| Process and IPC overhead | Fewer processes and fewer internal IPC paths; domains can call through in-process ports. | Each boundary adds process management and communication machinery. |
| Shared resource use | One address space and one coordination point for memory, accelerators, and device handles. | Resources are separated by process boundaries and may need explicit coordination. |
| Startup and deployment | One executable and one release lifecycle. | Components can be started, configured, and released independently, but operations are more involved. |
| Failure isolation | A fatal error can take down the complete application. | A failed component can potentially be restarted without stopping every component. |
| Independent scaling | Scaling is at the process or device level. | Distinct services can be scaled separately where the platform supports it. |
| Security boundaries | Domains share one process privilege and memory boundary. | Separate processes can create stronger containment boundaries. |
| Portability | Adapters can hide SoC-specific SDKs while retaining one binary shape. | Each service can carry its own runtime and deployment choices, with more integration work. |
Tauri’s official process-model documentation uses the general resilience argument that a crash in one component need not affect the whole system. An ADLINK/Vortex OpenSplice white paper describes bundled single-process deployment as potentially useful for embedded platforms. An OMICRON Lab application note similarly presents single-process software as potentially simpler and less demanding on CPU or memory while warning that interference can spread and an unrecoverable error can bring down the entire application. These documents frame the trade-off; they are not measurements of paiEngine.
When should an edge-AI team choose process separation?
Separate processes are justified when recovery, security, or deployment needs outweigh the overhead of additional runtimes and IPC. The ADR does not state the platform’s service-level objectives, threat model, or recovery targets, so the decision cannot be declared universal.
Choose isolation when failures must be contained
If audio capture, inference, or a third-party native SDK can fail independently, an independently supervised process may allow that component to restart while the rest of the device remains available. This is especially important when a fault-prone driver or untrusted parser sits on a security-sensitive path.
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Choose separate release units when cadence differs
A component that must be updated, rolled back, or A/B tested independently of the rest of the firmware is a candidate for its own process. The same applies when teams, compliance controls, or field rollout schedules differ.
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If one workload can consume all available CPU, memory, or accelerator time, a process boundary can make resource limits and supervision more explicit. It still cannot create capacity the device does not have, but it can make admission control and restart policy easier to enforce.
Choose separation for a hard security boundary
Domains sharing one address space also share the process’s privilege boundary. When a component handles untrusted input or requires materially different privileges, process isolation may reduce blast radius. The design must still be reviewed for kernel, driver, and IPC exposure; a process split is not a complete security model.
How can you decide whether one process fits your own platform?
Use a requirement test before selecting a topology. A single executable is a strong candidate when most answers fall in the first column.
| Question | Favors one process | Favors multiple processes |
|---|---|---|
| Do components ship together? | One device image and one coordinated release. | Independent rollout, rollback, or ownership. |
| Do they share scarce resources? | Frequent coordination of the same memory, accelerators, and peripherals. | Strict per-component quotas or conflicting resource profiles. |
| What happens after a component crash? | Whole-device restart is acceptable and fast. | Core functions must continue while one component recovers. |
| Is a privilege boundary required? | Components have similar trust and privilege needs. | Untrusted or high-risk code needs containment. |
| Is internal latency sensitive? | In-process calls and shared state simplify the hot path. | Isolation matters more than communication overhead. |
| Can the team maintain adapters? | Hardware and protocol changes can be isolated behind well-owned ports. | Boundaries are unclear or independent teams need autonomous services. |
Record the answers as architecture requirements, then test the chosen design on the exact board, memory size, drivers, and workload mix. Do not infer a win from the topology alone.
What pitfalls can undermine a modular monolith?
- Blocking the async runtime: running inference directly on an async worker can starve API and control tasks. Route long operations to dedicated threads and short blocking calls through
spawn_blocking. - Leaking hardware dependencies: importing an SoC SDK throughout domain code makes future hardware changes expensive. Keep SDK calls inside adapters.
- Creating a “big ball of mud”: one binary is not a license for unrestricted cross-module access. Enforce crate visibility, trait-based ports, and composition-root wiring.
- Ignoring whole-process failure: add watchdogs, health checks, crash recovery, and state reconstruction appropriate to the device. A modular boundary does not restart a failed process by itself.
- Assuming abstraction is free: ports and adapters add maintenance and testing surfaces. Keep interfaces narrow and tied to real variation points.
- Claiming performance without measurement: startup, memory, latency, and throughput depend on board configuration, drivers, model sizes, and scheduling. Benchmark those variables rather than repeating architectural assumptions.
What does the available evidence establish—and what remains open?
The architecture record establishes a documented design: one Rust executable, explicit domain crates, adapter-based hardware integration, a Tokio-plus-dedicated-thread execution model, and a hybrid NPU/CPU/GPU inference plan targeting RK3588 first. It does not establish benchmark improvements, a specific commercial board, or universal superiority over microservices.
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Before presenting the decision as settled, confirm four items: that paiOS/paiEngine is the platform intended by the headline; measurements on the target hardware; the exact RK3588 board and software configuration; and requirements for failure recovery, security isolation, and independent deployment. Those facts determine whether the documented rationale survives contact with the actual product.
What is the practical conclusion for an edge-AI architecture?
Rejecting microservices can be a disciplined choice when the product is one constrained device, components share resources, and releases move together. Rust’s traits, module visibility, and Cargo workspace can preserve replaceable boundaries inside that one process. The price is concentrated failure, shared privilege, and less freedom to restart, scale, or release components independently.
For an architecture like the one in ADR-004, the safest implementation path is to keep domains isolated in code, put every hardware and protocol integration behind an adapter, keep blocking inference off the async event loop, and validate the rationale with target-device measurements. If recovery or security requirements demand independent containment, introduce process boundaries where they solve that requirement rather than splitting the system by fashion.
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Frequently Asked Questions
Can a Rust modular monolith be split into services later?
Often, yes, if domain interfaces, data ownership, and adapter boundaries remain explicit. A later split still requires designing network contracts, serialization, service discovery, supervision, and deployment automation; a trait boundary is not automatically a production service API.
Does using Tokio make inference asynchronous?
No. Tokio coordinates asynchronous tasks, but a model invocation or native accelerator call can remain blocking. It must be moved to a dedicated thread or an appropriately bounded spawn_blocking operation so async workers continue serving I/O.
Is an RK3588 development board guaranteed to run this architecture?
No. RK3588 identifies the target SoC in the architecture record, not a verified board configuration. Board RAM, accelerator drivers, SDK versions, peripherals, and operating-system support must be checked before treating a particular board as compatible.
What is the first recovery mechanism to add to a single-process edge device?
Use an external supervisor or hardware watchdog that can restart the executable, then make startup idempotent and persistent state recoverable. That improves availability after a crash but does not provide the same in-process fault containment as separate services.
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