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JTAG and IJTAG address different layers of chip testing and access. JTAG usually refers to the IEEE 1149.1 Test Access Port (TAP) and its boundary-scan architecture, commonly used to test board interconnections and access device test logic. IJTAG is the industry name for IEEE 1687, a methodology and on-chip network for accessing embedded instruments such as monitors, sensors, debug blocks, and built-in self-test logic.
They are complementary, not competing standards. An external IEEE 1149.1 JTAG TAP can act as the doorway into an IEEE 1687 IJTAG network, but a JTAG port does not automatically mean that a chip supports IJTAG.
The short version
| Question | JTAG / IEEE 1149.1 | IJTAG / IEEE 1687 |
|---|---|---|
| What problem does it solve? | Standardized access to device test logic, boundary-scan cells, and selected device functions | Access and control of embedded instruments distributed inside a semiconductor device |
| What is the main target? | Device pins, package connections, board interconnects, and classic test structures | Internal monitors, sensors, debug blocks, DFT logic, diagnosis logic, and other reusable instruments |
| What is the central architecture? | A Test Access Port, instruction register, data registers, and boundary-scan register | An internal instrument-access network plus descriptions and procedures for operating instruments |
| Is it a physical connector? | The TAP is an electrical/logical interface commonly exposed through JTAG pins or a test header | No. IJTAG is not an “internal JTAG connector”; it is an on-chip access methodology and network |
| How do they relate? | Can provide the external access path | Can use an IEEE 1149.1 TAP as a gateway, while also supporting other specified digital interfaces |
In practical terms, ask:
- “Can I test these pins or board traces through the TAP?” That is primarily an IEEE 1149.1/JTAG question.
- “How do I reach and operate this monitor or diagnostic block inside the SoC?” That is primarily an IEEE 1687/IJTAG question.
When both questions apply, the accurate answer is that the chip uses an IEEE 1149.1 access port to reach an IEEE 1687 internal instrument network.
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IEEE 1149.1 standardizes test logic that can be built into an integrated circuit. Its scope includes testing interconnections between chips after they have been assembled on a PCB or another substrate, testing the device itself, and observing or modifying selected circuit activity during normal operation.
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The best-known part of the standard is boundary scan. Boundary-scan cells are placed near device pins so that digital signals can be captured, driven, or observed through test logic rather than only through physical probes. A test system can use those cells to check whether digital connections between devices behave as expected.
This is especially useful on dense boards and fine-pitch or BGA packages. Many pins cannot be reached conveniently with a probe, but a boundary-scan test can often control one device’s output and capture the resulting value at another device’s input.
The JTAG Test Access Port
A typical IEEE 1149.1 implementation exposes a serial test interface containing:
- TCK: test clock
- TMS: test mode select, used to control the TAP state machine
- TDI: serial test data input
- TDO: serial test data output
- TRST: an optional test-reset signal in many implementations
Multiple devices can be connected in a serial daisy chain. TDO from one device feeds TDI of the next, allowing a test controller to address the chain as a combined serial path.
The TAP controller uses TCK and TMS to move through states. A controller can shift an instruction into the instruction register, select an associated data register, and then shift test data into or out of that register. The test controller may be automatic test equipment, a development tool, a programming tool, or another bus master.
Common IEEE 1149.1-related structures include the boundary-scan register and bypass paths. The exact instruction set and optional features depend on the device implementation. A device description such as a BSDL file can tell test software about the device’s boundary-scan cells, pins, instructions, and chain-related details.
What people also mean by “JTAG”
“JTAG” is overloaded in engineering conversations. It can mean:
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- The historical Joint Test Action Group work that led to the technology.
- The IEEE 1149.1 TAP and serial test protocol.
- A physical test header or connector on a board.
- A programmer, debugger, test cable, or vendor-specific tool using a JTAG-compatible access mechanism.
These meanings are related but not interchangeable. A board labeled JTAG does not automatically provide full boundary-scan testing, processor debugging, FPGA programming, or IJTAG access. Those capabilities depend on the silicon, its implemented instructions and registers, the board wiring, voltage levels, device documentation, and tool support.
What IJTAG and IEEE 1687 define
IJTAG is the commonly used name for IEEE 1687, formally titled IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device.
IEEE 1687 addresses the problem of accessing many internal instruments in a complex chip. An instrument can be a monitor, sensor, performance counter, debug block, built-in self-test controller, diagnosis circuit, or another piece of design-for-test or design-for-debug IP.
The standard does not define what every instrument must measure or how every monitor must behave. Instead, it standardizes the way instruments can be connected, described, selected, and operated.
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- Access architecture: an on-chip network connects access points to embedded instruments. The path may be organized hierarchically and may be configured differently depending on the instrument being accessed.
- Hardware description: descriptions represent instrument connectivity, network behavior, and relevant interfaces so that tools can understand how to reach the instrument.
- Procedural and software description: procedures describe how to communicate with and operate a particular instrument—for example, how to configure it, trigger it, read its result, or reset it.
This separation is the key difference from classic boundary scan. Boundary scan is strongly associated with standardized test logic at the device boundary and with testing connections between devices. IJTAG is designed for a potentially large and reusable collection of internal instruments that may be scattered throughout an SoC and have no direct relationship to package pins.
How JTAG and IJTAG work together
A modern SoC can contain both architectures. Its external pins may expose an IEEE 1149.1 TAP. That TAP can provide ordinary 1149.1 functions, such as selecting a boundary-scan register, while also serving as the entry point to an IEEE 1687 network.
A simplified access sequence looks like this:
- A test or debug tool connects to the device’s supported external interface, often TCK, TMS, TDI, and TDO.
- The tool uses the IEEE 1149.1 TAP to enter the required test-access states and select an access path.
- The access mechanism reaches the chip’s IJTAG network.
- The IJTAG network selects or configures the path to a particular embedded instrument.
- An instrument procedure configures, triggers, reads, or resets that instrument.
- The result returns through the internal network and, where applicable, through the external TAP.
The exact registers, instructions, network elements, and procedures are implementation-specific. The important point is the layering:
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- External access layer: TAP signals and serial protocol, often supplied by IEEE 1149.1.
- Classic test-logic layer: the instruction register, data registers, boundary-scan register, bypass structures, and related test logic.
- Internal access layer: the IEEE 1687 network that routes access to embedded instruments.
- Instrument-operation layer: procedures for configuring and using a particular monitor, sensor, diagnostic block, or test controller.
IEEE 1687 allows its well-specified digital interfaces to be hosted under an IEEE 1149.1 TAP and also describes access through other specified digital interfaces. Therefore, IJTAG is not a replacement connector and is not necessarily tied to one particular external pinout.
Why boundary scan is not the same as IJTAG
Boundary scan primarily provides digital controllability and observability at or near the device boundary. Its classic job is structural testing: drive known values onto device pins, capture values at other pins, and identify likely open or shorted board connections under the implemented test conditions.
IJTAG addresses a different access problem. An internal instrument might be located deep inside a processor, connected to an on-chip clock, power, memory, or interconnect subsystem, and never connected directly to a package pin. Reaching it requires internal routing, selection, and repeatable operating procedures.
For example:
- A boundary-scan test might drive a digital output on one packaged device and verify that a neighboring device captures the expected value.
- An IJTAG procedure might select an on-chip temperature monitor, configure its measurement mode, start a reading, and retrieve the result.
- A JTAG-based programming operation might load an FPGA or microcontroller through device-specific programming logic. That is a practical use of a JTAG access path, but it is not automatically an IJTAG operation.
Boundary scan also should not be treated as complete functional or analog coverage. Its effectiveness depends on what the device and board actually implement. It is primarily a structural digital technique, not a universal replacement for functional tests, analog measurements, or system-level validation.
Why IEEE 1149.1 alone was not enough for large internal-instrument networks
Traditional 1149.1 usage centers on a device-level test-access structure and defined data registers. That works well for standardized boundary scan and related test functions, but a complex SoC may contain many instruments whose access paths need to be selected, bypassed, or reorganized.
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Early IJTAG work identified two important limitations when trying to use 1149.1 alone for this broader problem:
- Traditional 1149.1 data-register arrangements were treated as fixed-length structures rather than as a flexible description of a changing internal instrument network.
- IEEE 1149.1 by itself did not provide a complete standard way to describe an internal scan network and the procedures for operating the instruments connected to it.
That is the motivation for IEEE 1687—not a claim that IEEE 1149.1 cannot be extended or combined with other mechanisms. IJTAG adds the network-description and instrument-procedure concepts needed for scalable internal access.
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Is IEEE P1687 the same as IEEE 1687?
Not exactly. The published standard is IEEE 1687-2014. IEEE also lists an active P1687 revision project intended to supersede the 2014 standard, with PAR approval dated March 24, 2022.
Use the terms precisely:
- IEEE 1687-2014: the published standard for access and control of embedded instrumentation.
- IEEE P1687: the active revision project designation.
- IJTAG: the common industry name for this standard family and methodology.
The status and final designation of a standards revision can change. For a design or procurement decision, check the current IEEE project and publication status rather than assuming that a draft or project designation is already a ratified replacement.
Practical examples
Example 1: Testing a PCB connection
A board contains two devices connected by a digital bus, but their fine-pitch packages make physical probing difficult. A boundary-scan tool can use the devices’ TAPs and boundary-scan cells to drive test values from one device and capture them at the other. This is a classic IEEE 1149.1 use case.
Example 2: Programming an FPGA
An FPGA may expose a JTAG interface used to load configuration data. This is commonly called JTAG programming, but the programming instructions and configuration registers are device-specific. A generic JTAG cable is not guaranteed to program every FPGA.
Example 3: Reading an internal monitor
A system-on-chip contains voltage monitors, performance counters, and built-in self-test controllers. An IJTAG network can provide a structured way to reach those instruments without requiring each one to have a dedicated external pin. A supported external TAP may be the transport into the network, while IEEE 1687 descriptions and procedures tell the software how to select and operate each instrument.
Example 4: Processor debugging
A microcontroller may use a JTAG-compatible access port for processor debug. Debug support can coexist with boundary scan and other test functions, but the presence of a JTAG header alone does not prove which debug features are enabled. Consult the processor reference manual and supported debug-tool documentation.
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Use JTAG or IEEE 1149.1 when discussing:
- The TAP state machine and serial test signals
- Boundary-scan cells and boundary-scan registers
- Testing PCB interconnections
- Device-level test instructions and data registers
- Common JTAG-based programming or debugging, when the device supports it
Use IJTAG or IEEE 1687 when discussing:
- A network of instruments embedded inside an SoC
- Internal instrument connectivity and routing
- Reusable monitors, sensors, debug blocks, or DFT IP
- Descriptions of an internal access network
- Procedures for configuring, triggering, reading, or resetting instruments
Use both when an external 1149.1 TAP provides access to an internal 1687 network. Saying only that the chip “uses JTAG” may describe the physical entry point while hiding the internal architecture; saying only that it “uses IJTAG” may hide how the tool reaches the chip.
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What you need before buying hardware or choosing software
The standards distinction matters when moving from a conceptual explanation to an actual test setup. Before selecting a cable, programmer, or test platform, verify:
- The device’s implemented TAP signals, voltage levels, reset behavior, and maximum supported clock rate
- The device instruction set and supported data registers
- Whether boundary scan, programming, processor debug, or IJTAG access is actually implemented
- The correct BSDL and any vendor-specific description files
- The complete chain topology, including device order and bypass behavior
- Whether the software understands the device’s internal instrument network and procedures
- Whether the tool supports any vendor-specific extensions required by the device
A low-cost generic JTAG cable may be sufficient for a particular programming or debug task, but it is not automatically a complete boundary-scan tester and does not automatically provide IJTAG support. Professional board-test and diagnosis software can require device models, chain descriptions, supported procedures, and a compatible controller.
Go deeper on IEEE 1149.1
For readers who need a detailed treatment of boundary scan, BSDL, and IEEE 1149.1 implementation, The Boundary-Scan Handbook, 4th Edition is a useful professional reference. It is strongest as a boundary-scan and IEEE 1149.1 resource; it should not be treated as a substitute for the IEEE 1687 standard or the documentation for a specific IJTAG implementation.
Frequently Asked Questions
Does every JTAG port support IJTAG?
No. A JTAG port usually identifies an IEEE 1149.1-style access interface, but IJTAG support requires the chip to implement an IEEE 1687-compatible internal network and instruments, along with the necessary descriptions and tool support.
Is IJTAG a replacement for JTAG?
No. They are complementary. An IEEE 1149.1 TAP can provide external access to an IEEE 1687 internal instrument network, but IJTAG is not simply a newer JTAG connector or a faster version of JTAG.
Can JTAG program an FPGA or microcontroller?
Often, but only when that particular device implements JTAG-based programming logic and the selected tool supports it. “JTAG” alone does not guarantee programming, debugging, boundary scan, or any other specific function.
What does IJTAG standardize?
IEEE 1687 standardizes an access architecture for embedded instruments, ways to describe network connectivity and behavior, and procedures for communicating with and operating those instruments. It does not define a universal set of sensors, monitors, or instrument functions.
The Bottom Line
JTAG/IEEE 1149.1 is primarily the standardized external test-access and boundary-scan architecture; IJTAG/IEEE 1687 is the internal network and methodology for accessing embedded instruments inside a chip. A device can implement both, with the JTAG TAP acting as the entry point to IJTAG. Always verify the specific device, description files, instructions, and tool support before assuming that a labeled JTAG interface provides boundary scan, programming, debug, or IJTAG capability.
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