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RP2350-E9 is a conditional leakage-current problem in RP2350 A2 silicon—not a fault that affects every GPIO or every Pico 2. It can occur when a Bank 0 pad is configured as an input, its output is disabled, and its voltage sits between valid low and high logic levels. The practical first checks are therefore the chip stepping and the pad’s electrical state; a board’s “Pico 2” label alone does not identify its silicon revision.

What RP2350-E9 means

Raspberry Pi’s official erratum title is “Increased leakage current on Bank 0 GPIO when pad input is enabled.” It applies to RP2350 A2 and describes current sourced by a GPIO pad in a specific state. A symptom may look like a weak pull-down failing or a pin lingering at an unexpected voltage, but the formal issue is input-mode leakage—not a general latching defect.

The condition concerns GPIO pads 0–47 when all of the relevant conditions are present: input enable is set, output is disabled, the pad voltage is between VIL and VIH (the undefined logic region), and the specified isolation state applies. The current depends on the chip and pad voltage. At IOVDD 3.3 V, Raspberry Pi reports around 120 μA typical and says the pad can source current strongly enough to hold the voltage near 2.2 V. At IOVDD 1.8 V, the datasheet gives around 30 μA peak. These are condition-specific figures, not guaranteed readings for every pin or chip.

The internal pull-down is significantly weaker than the leakage in the affected state. Conversely, the internal pull-up still works and can pull a floating signal high out of the problematic voltage range. A strong source, such as a strong potential divider, can nevertheless hold the pad in the affected condition. QSPI pads and USB PHY pins are unaffected. SWD pads use the same pad macro, but Raspberry Pi says there is no ill effect because they are pulled up by default.

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These definitions and electrical figures appear in Appendix E, RP2350-E9, of the RP2350 datasheet, updated 2 October 2026 according to Raspberry Pi’s product portal.

How to tell whether a board has affected silicon

The erratum is tied to the chip stepping, not simply to a product name. Raspberry Pi’s datasheet identifies A2 as affected and says A3 fixed E9. In a 29 July 2025 announcement, Raspberry Pi said A4 also fixes the issue, described A3 as an intermediate qualification stepping, and reported that production had moved from A2 to A4 by that time. The announcement also said roughly 30,000 A3 units would be used in Pico 2 and Pico 2 W products and that all Pico 2 products would eventually use A4. Those are historical transition statements, not a guarantee about the stepping in a particular board purchased today.

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Identify the silicon revision in the specific unit before deciding whether an E9 workaround is needed. Raspberry Pi’s datasheet describes checking the package markings or reading the revision register. The Pico 2 product page establishes that Pico 2 is RP2350-based hardware, but the product name alone does not establish whether an individual board contains A2, A3, or A4 silicon.

Workarounds for A2 designs

For a design that needs pull-down behavior on affected A2 silicon, Raspberry Pi recommends clearing the pad’s input enable so the internal pull-down can pull the signal low. If the firmware needs to sample the pin, it can enable input immediately before the read and disable it immediately afterward. If the pad is already at logic 0, re-enabling input does not disturb the pull-down.

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  • Firmware-controlled input: Disable input except while sampling, where the application’s timing and signal behavior allow it.
  • External pull-down: Use 8.2 kΩ or less to overcome the leakage, as specified by Raspberry Pi. Whether this is appropriate depends on the rest of the circuit and its acceptable loading.
  • PIO-constrained designs: PIO programs cannot toggle pad controls. Depending on the application, an external pull may therefore be needed.
  • ADC use: If ADC channels are used on a pin, the datasheet directs the reader to clear the relevant GPIO input enable.

Raspberry Pi CEO Eben Upton wrote in the 29 July 2025 announcement that, on the fixed stepping, “external resistors are no longer required to pull inputs low, though they may safely be retained in existing designs.” That statement applies to the fixed silicon discussed in the announcement; it is not a reason to assume an unidentified board is fixed.

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What changed in the erratum’s description

Descriptions of the problem can emphasize a pull-down or pin-voltage symptom, which is useful when searching for a board-level behavior. The datasheet’s formal description is more precise: increased leakage current occurs when the Bank 0 pad input is enabled under the stated conditions. That framing explains why an internal pull-down may appear ineffective and why the issue is conditional rather than a blanket failure of GPIO pins.

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For a design review or bug report, record the stepping, GPIO number, IOVDD, pad voltage, source impedance, whether input enable remains set, and whether output is disabled. Also note whether PIO or ADC use constrains a firmware workaround and whether an external low-impedance pull-down is acceptable. These details distinguish an E9-compatible symptom from a broad claim that every A2 pin or every Pico 2 board is defective.

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