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On May 19, 2003, Mentor Graphics announced Precision RTL, a new FPGA logic-synthesis tool positioned as the next step after Leonardo Spectrum. Mentor said it kept Leonardo’s Verilog and VHDL parsers but rebuilt the rest of the synthesis technology, especially its algorithms, to target newer FPGA architectures. The announcement offered both push-button and interactive workflows; its speed and accuracy advantages were vendor claims, not independent benchmark findings.
What Mentor announced in May 2003
Precision RTL was intended to generate FPGA logic-synthesis results for newer devices and address increasingly complex timing and power demands, including designs with multiple timing and power domains. Mentor described its timing analysis engine as ASIC-quality, a product characterization rather than an independently validated comparison.
Simon Bloch, then general manager of Mentor Graphics’ FPGA Design division, explained the continuity and change: “The Leonardo parsers are good and very popular, so we reused those, but everything else — especially the algorithms — are new and are targeted for newer FPGAs.” EE Times reported the announcement on May 19, 2003.
How Precision RTL differed from Leonardo Spectrum
| Area | What Mentor described in 2003 |
|---|---|
| Language front end | Verilog and VHDL parsers from Leonardo Spectrum were retained. |
| Synthesis implementation | Mentor said the remaining technology, particularly the algorithms, was new. |
| Target context | The tool was aimed at newer FPGAs and the timing and power demands of multiple domains. |
| Workflow | Both an automated push-button approach and interactive controls were described. |
Bloch summarized the intended range of users: “The tool accommodates the needs of mainstream users with a push-button approach and high end users with interactive capabilities.” These design goals do not by themselves establish comparative quality, speed, or accuracy.
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- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
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What the related Precision Synthesis platform added
A Summer 2003 article by Tom Hill, Mentor’s Precision Synthesis product manager, described capabilities of the broader Precision Synthesis platform. Those platform-level details help explain the product family, but should not be treated as a feature-by-feature specification of the May announcement’s Precision RTL release.
- Constraint-driven setup: The described push-button flow selected synthesis configuration based on the design and its constraints, using Synopsys Design Constraint (SDC) format.
- Architecture Signature Extraction (ASE): These optimizations targeted likely bottlenecks, including finite-state machines, cross-hierarchical paths, and paths with excessive combinational logic.
- PreciseTime analysis: The article described internal-clock, missing-constraint, and asynchronous clock-crossing reports, along with critical-path visualization.
Hill’s Summer 2003 Xcell Journal article framed intuitive interaction, quality of results, and advanced analysis as design priorities. Those are the platform’s stated aims, not independent performance findings.
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RTL synthesis versus placement-informed physical synthesis
Precision RTL addressed logic synthesis. A separate product, Precision Physical Synthesis, added placement information to the optimization flow. In a December 2003 account, the flow synthesized a design to gates, received an initial placement from Xilinx or Altera tools, optimized the netlist using that placement information, and returned an improved netlist and placement to the vendor tools for implementation.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsThis distinction matters: the report describes a placement-informed synthesis flow, not a replacement placement tool. It also includes legacy device-family and support-planning details that were specific to that period, not guidance for current FPGA compatibility. Jeff Wilson, then Precision Physical Synthesis product-marketing manager, said users relying on logic synthesis alone could make “30, 40 or 50 iterations just to hit timing.” That was an attributed vendor observation, not a general benchmark. EE Times published the account on December 1, 2003.
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Leonardo migration and support terms at the time
Mentor planned to continue supporting Leonardo Spectrum device support but said it would not add new design technologies to that product. The May 2003 announcement reported different migration terms by Leonardo Spectrum level: level 3 users could move to Precision RTL at no extra cost, while level 1 and 2 users would pay more. The announcement also gave a starting price of $16,000 for Precision RTL. These are historical terms and pricing reported in 2003, not current offers.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Later product claims and today’s availability caveat
Mentor’s 2010 announcement for Precision Synthesis 2010a described assured synthesis for formally verifiable optimizations, integrations with Mentor verification and design products, low-power synthesis, and encryption. It claimed a 12% average performance improvement and improvements of up to 30% for some device families. Those figures are Mentor’s claims about the 2010a release, not measurements of the 2003 Precision RTL tool. The announcement listed a starting price of approximately $21,000 in 2010, not a current price. Mentor’s 2010 announcement.
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An Altera EDA partner directory currently lists Precision RTL, Precision RTL Plus, and Precision Physical by function. A directory entry confirms the names appear in that listing; it does not establish that the 2003 release can be purchased or licensed today, what current devices it supports, or its support lifecycle. The current Altera EDA partner directory is not a compatibility or availability guarantee.
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