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Choose an NVIDIA GPU when your project depends on CUDA, custom kernels, mature third-party tools, graphics or HPC libraries, or deployment outside Google Cloud. Choose a Google TPU when a dense, matrix-heavy model compiles cleanly with XLA and your team can use JAX, TensorFlow, or PyTorch/XLA. Neither accelerator is universally faster or cheaper: the right choice depends on end-to-end throughput, latency, memory fit, software-porting work, capacity, and the complete cloud bill.
This guide explains the architectural and operational differences, identifies workloads that fit each platform, and gives a repeatable benchmark process. Peak FLOPS alone are not a reliable predictor of cost or production performance.
What are Google TPUs and NVIDIA GPUs designed to do?
Google describes Tensor Processing Units as custom-developed, application-specific integrated circuits (ASICs) designed to accelerate machine-learning and artificial-intelligence workloads. TPU systems combine TensorCores for matrix operations, SparseCores for sparse workloads, high-bandwidth memory (HBM), inter-chip interconnects (ICI), and pod slices. Google’s GPU guidance describes NVIDIA systems built around programmable GPUs with Tensor Cores, HBM, and NVLink, giving them a broader role across AI, graphics, simulation, and high-performance computing.
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Which AI workloads fit a TPU or a GPU best?
Use the workload’s computation pattern and software dependencies as the first filter. The following mapping reflects Google’s current guidance rather than a universal benchmark.
| Workload or requirement | Usually the stronger starting point | Reason |
|---|---|---|
| Very large pre-training runs | TPU7x or TPU v5p; B200 or H200 GPU systems | These families provide large pods or tightly connected multi-accelerator systems for distributed training. The best result still depends on model parallelism and collective-communication efficiency. |
| Fine-tuning and batch inference with dense transformer graphs | TPU v6e or TPU7x | Google positions v6e for cost-efficient fine-tuning, serving, and batch inference, while TPU7x targets larger training and fine-tuning. |
| Low-latency, large-model serving | H100, H200, or B200 GPU systems; TPU7x can also fit a compiled serving graph | GPU systems offer large HBM capacities, NVLink, and broad serving-tool support. A TPU is competitive when the graph compiles cleanly and the service can use a TPU pod slice. |
| Models with custom CUDA kernels or rapidly changing operators | NVIDIA GPU | CUDA and the GPU ecosystem provide established paths for custom operators and specialized libraries. |
| Frequent branching, element-wise-heavy code, CPU-dependent paths, or substantial FP64 scientific work | NVIDIA GPU | Google identifies these patterns as potential TPU weaknesses because they reduce compiler efficiency or require fallbacks. |
| Graphics, mixed AI/HPC pipelines, or deployment across multiple clouds and on premises | NVIDIA GPU | GPU software and hardware are available across more environments and support non-ML workloads as well as ML. |
For embeddings and dense transformer layers, a TPU is a strong candidate if XLA can compile the complete graph. For irregular recommendation logic, simulation, or a research codebase that changes weekly, a GPU’s flexibility can outweigh a TPU’s accelerator efficiency.
How do TPU and GPU memory and bandwidth compare?
HBM capacity determines whether parameters, optimizer states, activations, and inference KV cache fit without expensive sharding or offloading. Bandwidth affects how quickly an accelerator can feed matrix units, but it does not by itself predict model throughput.
| Accelerator | Precision throughput listed by Google | HBM capacity | HBM bandwidth | Scale listed in the documentation |
|---|---|---|---|---|
| TPU7x | BF16: 2,307 TFLOPs; FP8: 4,614 TFLOPs | 192 GiB | 7,380 GB/s | 9,216-chip pod |
| TPU v6e | BF16/FP8: 918 TFLOPs | 32 GiB | 1,638 GB/s | 256-chip pod |
| NVIDIA H100 | Google’s cited machine table lists the model; the table does not provide a comparable TFLOP figure here | 80 GB HBM3 | 3.35 TB/s | GPU systems with NVLink |
| NVIDIA H200 | Google’s cited machine table lists the model; the table does not provide a comparable TFLOP figure here | 141 GB HBM3e | 4.8 TB/s | GPU systems with NVLink |
| NVIDIA B200 | Google’s cited machine table lists the model; the table does not provide a comparable TFLOP figure here | 180 GB HBM3e | 8 TB/s | GPU systems with NVLink |
The TPU figures are per TPU device as presented in Google’s current TPU documentation; the pod size indicates the available scale, not the memory of a single chip. GPU memory is also per accelerator. A model that barely fits on one device can still perform poorly if replication, optimizer state, activation checkpoints, or KV-cache growth forces additional devices.
What should you calculate before choosing a device?
- Parameter memory at the selected precision, including a copy for each replica where applicable.
- Optimizer-state and gradient memory for training. Adam-style states can require several times the parameter footprint.
- Activation memory at the target sequence length and microbatch size.
- Inference KV-cache memory at the maximum context and concurrent request count.
- Sharding, padding, communication buffers, and checkpoint space.
Leave headroom for input pipelines and runtime allocations. If the calculation only fits with aggressive offload, benchmark the resulting data movement rather than comparing accelerator specifications in isolation.
Will a PyTorch model run on a TPU?
Often, but not automatically. PyTorch models must use the PyTorch/XLA path, and operations must be supported and compilable by XLA. A model written for CUDA may contain custom extensions, device-specific assumptions, or CPU fallbacks that require code changes.
Check framework and operator compatibility
- List every framework dependency: standard PyTorch, PyTorch/XLA, JAX, TensorFlow, CUDA extensions, and data-processing libraries.
- Identify custom operators, dynamic shapes, frequent Python-side branching, and operations that execute on the CPU.
- Run a representative training or serving step through XLA, not just a small unit test. Compilation can expose unsupported operations that do not appear in a smoke test.
- Measure compile time, recompilation frequency, and synchronization points. A graph that repeatedly recompiles can erase TPU gains.
- Compare numerical behavior at the intended BF16, FP8, or other precision and verify convergence against the GPU implementation.
JAX and TensorFlow generally offer the most direct TPU paths. PyTorch/XLA can work well for supported models, but porting effort should be treated as an engineering cost in the decision.
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- Third-Generation Tensor Cores - New Tensor Float 32 (TF32) precision provides up to 5X the training throughput over the previous generation to accelerate AI and data science model training without requiring any code changes. Hardware support for structural sparsity doubles the throughput for inferencing. Tensor Cores also bring AI to graphics with capabilities like DLSS, AI denoising, and enhanced editing for select applications.
- Third-Generation NVIDIA NVLink - Increased GPU-to-GPU interconnect bandwidth provides a single scalable memory to accelerate graphics and compute workloads and tackle larger datasets.
- 48 Gigabytes (GB) of GPU Memory - Ultra-fast GDDR6 memory, scalable up to 96 GB with NVLink, gives data scientists, engineers, and creative professionals the large memory necessary to work with massive datasets and workloads like data science and simulation.
What is the difference between NVLink/NCCL and TPU ICI?
Distributed performance depends on how quickly devices exchange activations, gradients, and parameter shards. NVIDIA systems use NVLink for high-speed GPU-to-GPU connections and commonly use NCCL for collectives. TPU pods use Google’s ICI fabric and pod-slice topology with XLA-managed collectives.
Topology must match the parallelism strategy. Tensor parallelism is sensitive to latency and bandwidth for every layer; pipeline parallelism is sensitive to stage-to-stage transfers; data parallelism stresses all-reduce bandwidth. A nominally faster accelerator can lose if the selected slice has insufficient bisection bandwidth, if the collective algorithm is poorly matched, or if the workload performs frequent small synchronization operations.
During a pilot, record collective time separately from compute time. Also test the exact device count and topology planned for production: scaling from one device to a full pod or NVLink-connected host is not linear.
Are TPUs cheaper than GPUs?
Hardware-efficiency indicators favor TPUs in the historical figures available here, but they are not a cloud invoice or a universal price-performance result. A Federal Reserve note published in 2026 reproduces Epoch AI release-date estimates of hardware cost per TFLOP/s:
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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minute| Accelerator | Release-date hardware cost per TFLOP/s | How to interpret it |
|---|---|---|
| TPU v6e | $4.68 | Directional hardware-economics signal reproduced by the Federal Reserve from Epoch AI. |
| TPU v7 | $5.64 | Directional hardware-economics signal reproduced by the Federal Reserve from Epoch AI. |
| NVIDIA B200 | $14.80 | Directional hardware-economics signal reproduced by the Federal Reserve from Epoch AI. |
| NVIDIA H100 | $25.27 | Directional hardware-economics signal reproduced by the Federal Reserve from Epoch AI. |
| NVIDIA H200 | $25.27 | Directional hardware-economics signal reproduced by the Federal Reserve from Epoch AI. |
These figures omit cloud markup, host CPUs, storage, networking, orchestration, idle time, support, engineering labor, and the cost of failed or preempted runs. They also compare a theoretical rate, not tokens per second, samples per second, or converged training time.
How should you build a real cost estimate?
- Price the exact cloud SKU, region, machine shape, attached host resources, storage, and network traffic.
- Apply committed-use, reservation, or spot terms only when your workload can tolerate their constraints.
- Include utilization. Paying for an accelerator that waits on input data or recompiles is not equivalent to paying for one doing useful work.
- Add porting, profiling, debugging, checkpointing, and on-call labor.
- Calculate cost to a fixed outcome: a trained model at a target quality, or a service that meets its latency and throughput SLO.
Google states that spot prices are dynamic and are commonly 60–91% below on-demand prices for many GPU types, with exceptions. The discount can materially change a GPU comparison, but preemption and capacity risk must be modeled with checkpoint and restart time.
NVIDIA’s H100 page cites an approximately $0.09-per-million-tokens result for GPT-OSS-120B at 66 tokens per second per user using vLLM, based on a vendor-linked April 2026 SemiAnalysis InferenceX result. That number applies to the named model, runtime, setup, and date; it is not a general H100 price guarantee and should not be compared with a TPU without reproducing equivalent conditions.
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- NVIDIA Volta GV100 Architecture — 4,608 CUDA Cores, 640 1st-Gen Tensor Cores delivering 14 TFLOPS FP32 and 112 TFLOPS deep learning performance for AI training, inference, HPC, and scientific computing workloads
- 32GB HBM2 ECC Memory — 900 GB/s Bandwidth — High-bandwidth memory on a 4096-bit bus with ECC error correction provides the memory capacity and throughput required for the largest AI models, simulations, and datasets
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- NVLink — Scale to 96GB Unified Memory — Connect two V100 GPUs via NVLink at 300 GB/s bi-directional bandwidth to scale GPU memory from 32GB to 96GB for larger AI training and HPC workloads
- Multi-Precision Computing — Supports FP64 (7 TFLOPS), FP32 (14 TFLOPS), FP16 (112 TFLOPS) and INT8 precision modes for flexible deployment across training, inference, and scientific simulation workloads
How do you run a fair TPU-versus-GPU benchmark?
A matched pilot is more informative than peak specifications. Freeze the workload before selecting hardware so that each platform is solving the same problem.
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- Inventory software. Mark CUDA kernels, JAX or TensorFlow code, PyTorch/XLA requirements, custom operators, data-loader behavior, and CPU fallback paths.
- Prove the memory fit. Account for parameters, optimizer states, activations, KV cache, replication, sharding, and checkpoint buffers at the planned device count.
- Match topology. Select an equivalent NVLink/NCCL GPU configuration or TPU ICI pod slice. Keep parallelism, communication precision, and gradient accumulation consistent.
- Warm up and measure steady state. Exclude one-time compilation from a serving metric, but record compile time and recompilation separately because they affect deployment and autoscaling.
- Collect the same metrics. Measure tokens per second, samples per second, time to reach the target quality, p50 and p95 latency, joules, accelerator utilization, host utilization, and total hourly cost.
- Repeat failure scenarios. Test a worker loss, preemption, checkpoint restore, scale-up delay, and quota limitation. Record how much useful work is lost.
- Price the outcome. Multiply measured resource time by the actual SKU price and add engineering and operational costs. Choose the platform with the lower cost for your required outcome, not the lower nominal hourly rate.
What operational risks differ between TPUs and GPUs?
Capacity and quotas
Large TPU slices and high-end GPU instances can be capacity-constrained. Verify regional availability, quota lead time, reservation options, and the maximum slice size before committing to an architecture. A design that needs one unavailable 256-chip or larger allocation may be less practical than a smaller, readily schedulable fleet.
Preemption and recovery
Spot capacity can reduce cost but introduces interruption risk. Use frequent, integrity-checked checkpoints, idempotent job launchers, and a restart path that restores optimizer state as well as model weights. Measure recovery time; a cheap interrupted run can cost more than an uninterrupted on-demand run if checkpoints are slow or incomplete.
Compiler and runtime changes
TPU performance can change with XLA and framework versions. Pin tested versions, keep compilation logs, and rerun a performance test when upgrading. GPU workloads also depend on driver, CUDA, kernel, NCCL, and serving-runtime versions, so maintain an equivalent compatibility matrix rather than assuming a hardware swap is isolated.
Team familiarity
A team experienced with CUDA profiling, NCCL tuning, and GPU schedulers may reach production faster on GPUs. A team already using JAX and XLA may reduce TPU porting time. Treat this familiarity as measurable schedule risk, not as a preference that belongs outside the business case.
Which accelerator should you choose for common scenarios?
You are training a large transformer from scratch
Start pilots on TPU7x or TPU v5p and on B200 or H200 GPU systems if both are available. Compare time to the same validation quality, including input-pipeline and collective time. TPU7x’s listed 192 GiB HBM and 9,216-chip pod address scale, while B200’s listed 180 GB HBM3e and 8 TB/s bandwidth provide a high-memory GPU option; neither specification replaces a matched run.
You are fine-tuning many models with a small team
TPU v6e is worth testing when your models are regular and can use XLA. GPUs are safer when models arrive with CUDA extensions, unsupported operators, or changing architectures. Include the time to make the first model work and the time to onboard the tenth model.
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You need an API with strict p95 latency
Test H100, H200, or B200 systems with your serving runtime and concurrency target. A TPU can win for a stable, compiled graph, but compilation, warm-up, batching behavior, and autoscaling must be measured. Report p50 and p95 latency separately and include model-load and scale-out time.
You run scientific or mixed AI/HPC workloads
Choose a GPU unless a TPU pilot proves that the required numerical methods and precision are supported without CPU detours. Google specifically cautions that substantial FP64 work can be a poor TPU fit.
What are the most common selection mistakes?
- Choosing by peak FLOPS: Theoretical rates ignore graph compilation, memory pressure, communication, input stalls, and convergence time.
- Benchmarking a toy model: A small example may compile while the production model triggers unsupported operations or different memory behavior.
- Ignoring custom code: A single CUDA extension or CPU fallback can dominate runtime after a port.
- Comparing hourly prices only: Include utilization, spot interruption, storage, network, and engineering work.
- Under-sizing inference memory: KV cache grows with context and concurrency; a model that fits at batch one may not fit at the service target.
- Assuming linear scaling: Validate the exact pod slice or NVLink topology and measure collective time.
- Skipping recovery tests: Capacity and preemption failures are operational costs, not edge cases to discover after launch.
What is the practical decision rule?
Select NVIDIA GPUs when portability, CUDA, custom operators, broad tooling, graphics or HPC support, and flexible deployment are primary requirements. Select Google TPUs when the workload is dense and regular, XLA compilation is reliable, the team can use JAX, TensorFlow, or PyTorch/XLA, and Google Cloud capacity and topology meet the deployment plan.
When both appear viable, run the same model and service or training target on each, then compare cost per completed outcome, not cost per accelerator-hour. Keep the benchmark harness and model revision fixed, publish the conditions with every result, and revisit the decision when model architecture, compiler versions, cloud pricing, or capacity changes.
Frequently Asked Questions
Can I train on a TPU and serve on an NVIDIA GPU?
Yes, if you export a portable model representation and verify numerical behavior and operator support on the serving stack. Re-test batching, precision, kernel availability, and latency because a checkpoint that trains efficiently on one platform may need different graph or runtime optimizations on the other.
Do TPUs support FP64 scientific workloads?
TPUs can execute some higher-precision operations, but Google identifies substantial FP64-heavy scientific work as a potential poor fit. If FP64 is central to the algorithm, benchmark the complete numerical method and any CPU fallback before selecting a TPU.
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How much code usually has to change when moving PyTorch from CUDA to TPU?
There is no reliable percentage: a standard-operator model may need modest device and input-pipeline changes, while custom CUDA extensions or dynamic control flow can require a substantial rewrite. The only dependable estimate comes from an operator inventory followed by a representative PyTorch/XLA run.
Are TPU pod slices available in every Google Cloud region?
Availability and quota vary by accelerator generation, slice size, and region. Confirm capacity and reservation terms for the exact TPU type and topology before designing a production deployment around a large pod slice.
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