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Choose the foundry that can deliver your complete AI system—not merely the smallest advertised transistor. Start with the workload, memory bandwidth, power limit, die and package dimensions, HBM or other memory interface, thermal envelope, production volume, and launch geography. Then make each candidate prove process-design-kit (PDK) maturity, silicon-proven IP, package and test feasibility, yield learning, wafer and assembly capacity, engineering support, and ramp commitments for your exact design. TSMC, Samsung Foundry, and Intel Foundry can all belong on a serious shortlist, but public node roadmaps and wafer prices cannot tell you which one is safest. A design-specific RFQ, equivalent PPA study, and contractual capacity plan are essential.
What should you decide before contacting a foundry?
Write a system specification that a foundry can evaluate. The specification should describe the product you intend to ship, not just the accelerator die.
Freeze the workload and performance target
- Define model types, batch sizes, arithmetic formats, target throughput, latency limits, utilization assumptions, and host-interconnect requirements.
- Set the power envelope for the die and for the complete package, including memory and voltage-regulation losses.
- Quantify memory capacity and bandwidth. An accelerator that has enough compute but cannot feed its arrays will not benefit from a denser process.
- State die-area limits, reticle constraints, expected chiplet partitioning, and whether the design requires one large die or several smaller dies.
Specify the package as part of the chip
Identify HBM generation and stack count, interposer or bridge requirements, package dimensions, thermal interface assumptions, mechanical limits, and test coverage. For an AI accelerator, interposer, assembly, thermal, and final-test capacity can constrain shipment more severely than transistor density.
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Give the foundry an initial wafer-start forecast, engineering-lot schedule, target production date, acceptable regions for wafer and package production, and any export-control, customer-residency, automotive, industrial, or government requirements. A process that is technically suitable but unavailable in your launch geography is not a practical choice.
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How do you choose the right process node for an AI accelerator?
The right node is the one that meets your complete PPA, SRAM, I/O, analog, voltage, and reliability requirements with a production-ready PDK and libraries. “More advanced” is not automatically faster, cheaper, or easier to ramp.
Compare the complete design envelope
| Requirement | Questions to ask | Why it can outweigh nominal density |
|---|---|---|
| Compute PPA | What frequency, voltage, power, and area can the foundry demonstrate on logic similar to yours? | Real workload performance depends on memory, interconnect, clocking, and power delivery as well as transistor density. |
| SRAM and embedded memory | Which SRAM bit cells, compiler options, redundancy features, and operating corners are production qualified? | Large local memories can dominate area, leakage, yield, and performance in an accelerator. |
| I/O and SerDes | Are the required PCIe, DDR, Ethernet, die-to-die, and HBM interfaces available at your speed and voltage? | A dense core is of little use if external bandwidth or signal integrity is inadequate. |
| Analog and mixed signal | Do the process options support clocks, sensors, power management, data converters, or other analog blocks? | Moving an analog-heavy design to an advanced logic node can add redesign and qualification work. |
| Reliability | What voltage range, electromigration rules, temperature grades, radiation data, and lifetime models apply? | Industrial, automotive, and datacenter deployments impose different qualification and derating requirements. |
Ask for evidence instead of a node label
Request benchmark results or reference designs that use comparable SRAM density, I/O, clock rates, and package conditions. Ask which PDK release, design rules, standard-cell libraries, extraction decks, timing models, and power models produced the results. Record the version and release date in the program plan; a future PDK revision can change rules, models, or signoff requirements.
Consider mature or specialty options deliberately
A mature node may offer better analog support, higher-voltage devices, wider I/O choices, established yield, or lower mask and wafer risk. A chiplet strategy can put dense compute on an advanced die while using a mature die for I/O, power management, or control. Evaluate that partition at package level rather than assuming every function belongs on the newest node.
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Why are the PDK, IP, and EDA ecosystem as important as the process?
Production-proven enablement reduces the probability that a theoretically suitable process turns into a late tape-out or a respin.
Check PDK maturity
- Confirm the exact PDK release available to your team, its known issues, change-control policy, and date for production signoff.
- Verify that physical-verification decks, extraction, timing, power integrity, electromigration, thermal, and reliability flows work with your chosen EDA versions.
- Ask whether reference flows have been used in volume production or only in demonstrations.
Audit critical IP
List every block that cannot be designed from scratch: HBM and die-to-die interfaces, SerDes, PCIe, DDR, security, clocking, memories, and standard-cell libraries. Confirm availability for your process and package, silicon history, errata, license scope, support ownership, and qualification data. An IP block that exists on a slide but is not released for your PDK is not available to the schedule.
Measure engineering support
Ask how many application engineers will support architecture, physical design, signoff, package co-design, and failure analysis; where they are located; and what escalation path exists during tape-out and first silicon. TSMC describes its Open Innovation Platform as using “silicon-verified, production-proven, and quality-assessed” IP and libraries to lower design barriers and improve first-time silicon success. Treat that as an ecosystem capability to verify for your exact IP list, not as a guarantee.
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How should packaging and HBM affect the foundry decision?
For many AI products, package feasibility is a first-order silicon-selection criterion. Select the wafer process and package stack together.
Evaluate the full 2.5D or 3D path
- Confirm interposer, bridge, die-stacking, microbump, hybrid-bonding, substrate, and lid options for the required die count and dimensions.
- Model HBM placement, power delivery, signal integrity, thermal resistance, warpage, and mechanical stress with the foundry and package team.
- Ask how package assembly, burn-in, final test, and known-good-die screening scale at your target volume.
- Establish who owns package design rules, thermal models, assembly yield, and failure analysis when multiple suppliers are involved.
Check capacity at the bottleneck, not just wafer capacity
A foundry may have wafer starts while its interposer, substrate, HBM integration, assembly, or test line is constrained. Require a package-capacity model with monthly slots, qualification gates, yield assumptions, long-lead materials, and a recovery plan for a site or supplier disruption.
Compare integrated and multi-supplier models
An integrated foundry/package/test offer can simplify accountability and qualification. A multi-supplier model may improve leverage or geographic resilience but adds interface ownership, logistics, and requalification work. Compare delivered good packages, not wafer cost in isolation.
Which foundries belong on an AI-chip shortlist?
Use the following public positioning as a starting point, then verify current availability, yield, package slots, and commercial terms through an NDA and RFQ.
| Foundry | Publicly described strengths | Questions that remain design-specific |
|---|---|---|
| TSMC | Pure-play scale, broad advanced and specialty processes, a large design ecosystem, and 3DFabric advanced stacking and packaging. | Can it allocate your wafer starts and package/test slots in the required geography and production window? What are the terms, yield milestones, and contingency sites for your program? |
| Samsung Foundry | Dedicated design platform covering libraries, PDKs, methodology, IP, design support, packaging, and cloud services; SAFE ecosystem alliances; MDI Alliance for 2.5D/3D heterogeneous integration. | Which PDK and IP versions are production proven for your blocks, and what package/test capacity and customer references apply at your volume? |
| Intel Foundry | A systems-foundry model spanning process, IP, EDA, advanced packaging, and Advanced System Assembly and Test (ASAT), with support for ARM, RISC-V, x86, and custom ASIC architectures. | What is actually available for your node and launch date, what yield and capacity evidence can be shared, and how will package, test, and geographic requirements be contracted? |
What the published TSMC scale figures do—and do not—prove
TSMC’s 2024 annual report describes “a full range of integrated semiconductor foundry services including leading advanced process and specialty technologies, advanced mask technologies, TSMC 3DFabric® advanced silicon stacking and packaging technologies excellent manufacturing productivity and quality, as well as comprehensive design ecosystem support.” The same report site lists 12.9 million 12-inch-equivalent wafer shipments, 69% of wafer revenue from 7nm-and-beyond technologies, 288 process technologies, 11,878 products, and 522 customers for 2024. TSMC’s 2025 figures list 12,682 products, 305 distinct technologies, and 534 customers. These are scale indicators, not a promise of allocation, yield, price, or package availability for a startup.
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What Intel’s systems-foundry model changes
Intel announced Intel Foundry on February 21, 2024, positioning it as a systems foundry for the AI era, with an expanded roadmap including Intel 14A, specialized nodes, and ASAT. Intel said Synopsys, Cadence, Siemens, and Ansys had validated tools, design flows, and IP for Intel 18A and advanced packaging. Its fact sheet describes a full-stack offer for systems of chips and support for ARM, RISC-V, x86, and custom ASIC architectures. Verify node release status, production yield, package qualifications, and customer references rather than treating a roadmap announcement as available capacity.
How to evaluate Samsung’s platform
Samsung says its design platform combines libraries, PDKs, design methodology, IP, design support, packaging, and cloud services. Its SAFE ecosystem includes IP, EDA, cloud, DSP, and OSAT alliances, while the MDI Alliance provides 2.5D/3D heterogeneous-integration packaging as a one-stop service. Ask for process-specific production references, package stack details, engineering support coverage, and committed capacity at your required volume.
What should a foundry RFQ include?
Public capability pages rarely provide comparable prices, guaranteed allocation, or customer-specific yield. Send the same technical and commercial package to each candidate so the responses can be compared on delivered system risk.
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| RFQ area | Required questions | Decision use |
|---|---|---|
| PPA and node | What benchmark results, SRAM choices, I/O, voltage range, and design rules apply to this workload? | Prevents paying for density that does not improve delivered performance. |
| PDK, IP, and EDA | Which PDK release, standard-cell libraries, SerDes/HBM/PCIe/DDR IP, and signoff flows are production proven? | Exposes immature enablement and respin risk. |
| Packaging | Which 2.5D/3D, interposer, chiplet, HBM, thermal, assembly, and test options are available at target volume? | Shows whether package or test—not wafers—will limit shipments. |
| Yield and ramp | What qualification gates, defect-density targets, known-good-die strategy, and time-to-volume assumptions apply? | Converts yield learning into usable-die cost and launch timing. |
| Capacity | Can wafer starts and package/test slots be reserved? What fallback sites and recovery times exist? | Protects against demand spikes and site disruption. |
| Economics | Quote masks and NRE, engineering lots, wafers, IP and EDA fees, package/test, expedite charges, minimum volumes, payment schedule, and cancellation terms. | Enables total-cost comparison instead of wafer-price comparison. |
| Geography and resilience | Where are wafers, packaging, test, reticles, and critical materials sourced? What export-control and disaster contingencies apply? | Reveals supply-chain exposure for globally distributed AI products. |
| Quality and security | Which automotive or industrial quality systems, traceability, secure-design controls, and confidentiality protections apply? | Determines suitability for regulated or strategic deployments. |
| Roadmap | What production date, customer qualification status, and migration path are committed in writing? | Separates contractual readiness from roadmap slides. |
How do you run a foundry selection step by step?
Run technical, operational, and commercial workstreams in parallel; delaying packaging or capacity questions until after tape-out creates avoidable risk.
- Freeze the system specification. Document performance, power, memory, die area, package, HBM, thermal limits, volume, launch geography, quality grade, and target dates.
- Shortlist two or three candidates. Eliminate any process or package that fails a hard requirement before spending engineering time on detailed studies.
- Open an NDA data room. Request the exact PDK maturity, IP releases, reference flows, yield history, package stack, engineering-support model, and capacity plan.
- Run equivalent design studies. Use the same architecture assumptions and, where possible, shuttle silicon to compare PPA, design effort, schedule, package feasibility, and risk-adjusted cost.
- Negotiate one integrated commercial package. Cover wafers, masks and NRE, engineering lots, package and test, capacity reservations, quality, change control, cancellation, expedite, and contingency terms together.
- Set stage gates. Gate PDK release, IP readiness, package signoff, tape-out readiness, first silicon, package qualification, yield milestones, and volume ramp. Keep a second-source or redesign contingency when its cost is justified by revenue and supply risk.
How should you score candidates without overvaluing the node?
Use a common scorecard, but keep non-negotiable failures separate from weighted preferences. A candidate that fails HBM package feasibility or launch capacity should not win because it offers a lower wafer quote.
- Hard gates: required PDK and IP release, interface support, package stack, thermal limits, quality requirements, export-control fit, and committed production window.
- Technical score: workload PPA, SRAM and I/O fit, design-rule complexity, power delivery, package signal integrity, and expected usable-die cost.
- Execution score: reference-flow maturity, application-engineer coverage, known-good-die and test strategy, qualification evidence, and change-control discipline.
- Supply score: wafer allocation, package and substrate slots, geographic redundancy, material exposure, and recovery commitments.
- Economic score: total risk-adjusted cost, including masks, engineering lots, IP and EDA, package/test, expediting, minimum volume, and the cost of a potential respin.
Keep the evidence behind every score: document owner, PDK version, date, assumption, and whether a statement is contractual, measured, or indicative. This prevents a polished roadmap presentation from receiving the same weight as a qualified production result.
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What are the most common foundry-selection mistakes?
Choosing by node name alone
A smaller geometry can increase mask complexity, design-rule burden, IP licensing, and power-delivery difficulty without improving your bottleneck. Measure complete package-level throughput, latency, power, and usable-die cost.
Treating packaging as a later procurement
HBM, interposers, substrates, thermal hardware, assembly, and test must be co-designed with the die. A late package change can force floorplan, bump-map, power, or signal-integrity changes.
Comparing wafer prices instead of delivered good packages
Include masks, NRE, engineering lots, IP and EDA fees, assembly, test, yield loss, expedite charges, minimum volumes, and inventory or cancellation exposure.
Assuming public roadmaps equal capacity
Roadmap dates do not establish your wafer-start allocation, package slots, qualification status, or recovery plan. Require dated commitments and escalation paths.
Underestimating portability
Standard cells, IP, timing, power delivery, package rules, and yield learning are tightly coupled to a process. Moving foundries can require substantial requalification and redesign; price a second source before assuming an easy switch.
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Ignoring geographic and security requirements
Map wafer, reticle, package, test, substrate, and critical-material origins. Confirm export-control handling, confidentiality, traceability, and secure-design controls before architecture is locked.
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What information is still unavailable publicly?
There is no public, universal ranking of AI-foundry process nodes, and the available company figures do not establish comparable prices, guaranteed allocation, or customer-specific yield. Those answers require a current, confidential RFQ and design-specific analysis. Treat every public capacity, ecosystem, or roadmap statement as a reason to investigate—not as a substitute for contractual evidence.
Frequently Asked Questions
Is the newest process node always the fastest choice for an AI chip?
No. Throughput can be limited by SRAM, HBM bandwidth, I/O, power delivery, thermal resistance, or package test capacity. A mature or mixed-node chiplet design can deliver better system performance and lower schedule risk when those are the real constraints.
Can a startup obtain advanced-node wafers and HBM-class packaging?
Access is negotiated and depends on PDK readiness, design qualification, forecast volume, wafer allocation, package qualification, and available assembly slots. Ask early about shuttle or engineering-lot paths, then obtain written commitments for production capacity; no public source guarantees access for a particular startup.
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Request the foundry’s qualification gates, defect-density targets, yield-learning milestones, known-good-die method, test coverage, and assumptions for a die of your size and complexity. Use those inputs to model usable packaged dies and cash exposure rather than relying on a single headline yield percentage.
Does supporting ARM, RISC-V, or x86 determine which foundry I should use?
It can narrow the shortlist when you need architecture-specific libraries, IP, or system support. Verify the exact core, interconnect, memory, security, and package IP releases for your PDK; architectural flexibility alone does not prove production readiness.
What happens if I need to change foundries after tape-out?
Expect more than a mask transfer: standard cells, physical libraries, timing and power models, package rules, IP licenses, signoff decks, and yield learning are process-specific. A second source is valuable only if its requalification cost and schedule have been planned before the first design is committed.
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