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A semiconductor fabrication facility (fab) builds integrated circuits as a stack of precisely aligned layers on a silicon wafer. Deposition, photoresist, lithography, etching, ion implantation, cleaning and inspection repeat hundreds of times. The wafer is then cut into dies, packaged and tested. Understanding that loop explains what a wafer is, what lithography actually does, why cleanrooms are so strict and why yield determines whether a process is economically viable.
What a semiconductor fab actually is
A fab is a factory for making the microscopic structures inside integrated circuits. It is not the same thing as a chip-design office, a packaging plant or a retail semiconductor company. In the front end of manufacturing, machines create transistors and the metal wiring that connects them on a flat silicon wafer. In the back end, the finished wafer is cut apart and each working piece is assembled into a package.
The work is sequential rather than a single printing operation. A modern chip may contain as many as 100 patterned layers, and every layer must line up with the ones below it to nanometer-scale tolerances. A complete production flow can involve hundreds of operations. ASML says the path from design to mass production can take up to four months, while Intel describes wafers passing through thousands of processing steps over several weeks before packaging. The exact time depends on the product, process and factory schedule.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchFabs also differ greatly in what they make. Some produce leading-edge logic; others specialize in mature-node analog, power-management, automotive, sensor or memory devices. A building with a cleanroom is a physical fab. A foundry is a business relationship in which that fab manufactures designs owned by customers.
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From refined silicon to a usable wafer
Growing a single crystal
Manufacturing starts with silicon refined to extremely high purity. The silicon is melted and formed into a single-crystal ingot. A single crystal gives engineers a uniform lattice in which electrical properties can be controlled consistently. The ingot is measured, inspected and prepared for slicing.
Slicing and polishing
A diamond saw cuts the ingot into thin circular discs. Sawing leaves microscopic damage and unevenness, so the discs are ground, chemically treated and polished until the surface is exceptionally flat and smooth. The finished disc is the wafer: a shared substrate on which many copies of a circuit are built in parallel.
Common wafer diameters
| Diameter | Approximate name | Where it fits |
|---|---|---|
| 300 mm | 12-inch wafer | Widely used for high-volume modern logic and memory |
| 200 mm | 8-inch wafer | Common in mature-node, analog, power and specialty production |
| 150 mm | 6-inch wafer | Used in some older or highly specialized processes |
TSMC’s company profile lists facilities using 12-inch, 8-inch and 6-inch formats. A larger diameter provides more area for dies in one pass, but it does not automatically make a product cheaper. Die size, edge losses, defect density, equipment cost and yield determine how many saleable chips result.
Every wafer carries alignment marks and identification information. The wafer is divided conceptually into a grid of rectangular dies, with partial dies near the edge often discarded. The same circuit pattern is exposed repeatedly across that grid. After all layers are complete, a diamond saw separates the wafer into individual dies.
The repeating wafer-process loop
Each layer follows a related sequence. The materials and recipes change, but the manufacturing logic stays recognizable: add a film, define a pattern, remove or modify selected regions, clean the surface and measure the result.
1. Deposition: adding a film
Deposition places a thin layer on the wafer. The layer may conduct electricity, insulate it or act as a semiconductor. Different tools use techniques such as chemical vapor deposition, physical vapor deposition or atomic-layer deposition, selected for the required thickness, composition and conformality. A film that is slightly too thick, too thin or non-uniform can affect every die on the wafer.
2. Photoresist coating
The wafer is dispensed with a light-sensitive material called photoresist and spun at high speed. Centrifugal force spreads the resist into a controlled film. A bake removes solvent and stabilizes the coating. Resist thickness, viscosity, spin speed and bake conditions influence how accurately the next pattern can be developed.
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3. Lithography exposure
A reticle, sometimes called a mask, carries the circuit pattern for one layer. Light passes through or reflects from the reticle, and precision optics reduce and focus that image onto the photoresist. The wafer stage moves through a series of exposure fields so the same pattern is printed across the wafer. Lithography does not create the final three-dimensional feature by itself; it creates a temporary chemical stencil.
4. Bake and develop
After exposure, a post-exposure bake drives the resist chemistry to completion. Developer solution then dissolves either the exposed or unexposed portions, depending on whether the resist is positive or negative. The result is a patterned resist layer with openings where an underlying film will be etched or where a later deposition must reach the surface.
5. Etch: transferring the pattern
Etch removes material through the resist openings. Dry etch uses a plasma of reactive gases and can make highly directional features. Wet etch uses liquid chemicals and may be preferable for selective, isotropic removal. Engineers control selectivity, sidewall shape, etch depth and damage to the layers underneath. Once the exposed film is removed, the resist pattern has become a physical structure.
6. Ion implantation: tuning silicon
Ion implantation accelerates charged dopant atoms into selected silicon regions. The dose and energy determine concentration and depth. Dopants change conductivity and create regions such as a transistor’s source and drain. A subsequent thermal treatment repairs lattice damage and activates the dopants. Implantation is one of the steps that turns a patterned silicon surface into an electrically functioning device.
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After pattern transfer, the remaining resist is stripped with plasma or chemicals. Wet cleans remove particles, residues and metallic contamination. Cleaning is repeated throughout the flow because a trace left on one layer can interfere with adhesion, etch selectivity or electrical reliability on the next.
8. Metrology and inspection
Optical and electron-beam tools measure critical dimensions, film thickness, overlay alignment and surface defects. Inspection systems search for particles, scratches and pattern failures. The measurements feed statistical process-control charts and recipe adjustments. If a trend moves toward a limit, engineers can correct the tool before many wafers are affected.
This loop is repeated for every transistor, contact and wiring layer. Some steps are performed once; others recur dozens of times. The wafer gradually changes from a polished disc into a dense vertical stack of electrical structures.
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What lithography does, in plain language
A lithography system is essentially a projection system. The reticle contains a pattern larger than the feature that will remain on the wafer. Reduction optics shrink the image, focus it and scan it over the resist. Development converts the exposure into openings, and etch or deposition uses those openings to form the layer.
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EUV and DUV roles
Extreme ultraviolet (EUV) tools are used for the smallest critical layers in advanced processes. Deep ultraviolet (DUV) tools handle larger features and many non-critical layers. A leading-edge fab therefore uses a mix of tools rather than replacing every exposure with EUV. The choice depends on feature size, layer criticality, throughput and the process design rules.
Computational lithography
Light diffracts, resist chemistry blurs edges and lenses introduce optical distortions. Computational lithography models those effects and deliberately pre-distorts the reticle pattern so the wafer result is closer to the intended geometry. Models are updated with data from exposure tools, test wafers and metrology. This correction improves process window and yield without changing the circuit’s logical design.
Overlay is as important as resolution
A layer can have the right line width and still fail if it is shifted relative to the previous layer. Alignment marks and stage-control systems measure and correct overlay error. Because modern chips may have up to 100 layers, a small systematic shift can accumulate into open contacts, shorted wires or transistors with the wrong dimensions.
Why fab cleanrooms are so controlled
A dust particle is enormous compared with a nanometer-scale line and can destroy a die. ASML describes semiconductor cleanrooms as about 10,000 times cleaner than outside air; many are designed around ISO Class 1 conditions. Air is filtered and recirculated, and wafers travel in sealed carriers rather than being exposed to ordinary room air.
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Particle control is only one part of the environment. Fabs regulate temperature and humidity so resist and chemicals behave consistently. Floors and tool foundations suppress vibration that could blur an exposure. Ultrapure water and high-purity gases prevent ionic or metallic contamination. Equipment is calibrated and maintained on scheduled intervals because a small drift can affect thousands of wafers before it becomes visible.
Operators wear protective garments to keep skin, hair and fibers out of the process area. Automated material-handling systems move carriers between tools, reducing both contamination risk and handling variation. These controls add substantial capital and operating cost, but they protect a process in which one microscopic defect can remove the value of an entire die.
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Yield: the number that turns wafers into products
Intel defines yield as “the percentage of usable die that are produced on a processed wafer.” A wafer can complete every scheduled operation and still contain a mixture of good and bad dies. Yield is therefore an economic scorecard, not merely a laboratory quality metric.
What lowers yield
- Particles, scratches and contamination that damage a die or prevent a layer from adhering.
- Film thickness or composition that drifts outside specification.
- Overlay errors between successive lithography layers.
- Line-edge roughness and critical-dimension variation.
- Etch damage, incomplete pattern transfer or implant dose errors.
- Unstable temperature, vibration, chemical purity or tool calibration.
- Defects that become more likely as die area increases.
Why there is no universal yield percentage
Yield varies by product, die size, defect density, process maturity and factory conditions. A small mature-node chip may tolerate a different defect environment from a very large leading-edge processor. Early production generally has lower yield while engineers tune recipes; yield normally improves as inspection data and process-control feedback identify recurring failure modes. A quoted percentage is meaningful only when its product, process, date and measurement method are stated.
How engineers improve it
Inspection locates defects and metrology measures their size and position. Statistical process control distinguishes random variation from a tool drifting toward a limit. Engineers correlate wafer maps with equipment, chamber, reticle and recipe history. Computational lithography narrows patterning errors, while preventive maintenance addresses recurring particle sources. The goal is not simply to discard bad dies at the end; it is to stop creating them earlier in the flow.
Wafer diameter affects the number of possible dies, but diameter alone does not determine economics. A larger wafer with poor yield can produce fewer saleable chips than a smaller, well-controlled wafer. Die area and defect density interact strongly: as die area rises, the chance that a random defect lands somewhere in that die also rises.
From front end to package: where a chip becomes a product
Front-end wafer fabrication
Front-end processing creates the transistors, contacts and interconnect stack on the wafer. It determines electrical characteristics such as switching speed, leakage, voltage tolerance and density. At the end of front end, each grid location contains a complete die, but it is still attached to its neighbors and has no external pins.
Dicing and die attach
A diamond saw or laser separates the wafer along its streets. Known-good dies are attached to a package substrate or lead frame. Dies that fail electrical or visual tests are excluded from assembly or marked for analysis.
Connections, protection and heat removal
Electrical paths from the die to the package may use wire bonds, flip-chip bumps or other interconnect structures. The package protects the silicon, routes signals to the circuit board and provides a thermal path. Lids, heat spreaders, underfill and mold compounds are selected for the product’s power and reliability requirements.
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Final test
Packaged parts undergo electrical, timing, thermal and reliability tests. Testing screens for defects introduced during assembly as well as those that originated in wafer fabrication. The package is part of the electrical and thermal design, not merely a container: its interconnect length, power delivery and heat resistance can limit the finished product.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Who operates a fab?
| Business model | What the company controls | Typical relationship |
|---|---|---|
| Integrated device manufacturer (IDM) | Designs chips and operates manufacturing capacity | One organization manages both product architecture and fabrication, though it may also use outside suppliers |
| Pure-play foundry | Manufactures wafers for customers’ designs | Customers provide the circuit design and process requirements; the foundry runs the fab |
| Fabless company | Focuses on architecture, verification and product development | Contracts wafer production and usually purchases packaging and testing services |
Intel and Samsung are examples of IDMs. TSMC, GlobalFoundries and UMC operate foundry businesses. Many processor and graphics designers are fabless. These categories can overlap in practice: an IDM may use a foundry for some products, and a foundry may offer packaging as well as wafer processing.
How to compare fabs or semiconductor processes
“Smaller node” is not a complete technical description. Intel describes a process node as a recipe and ingredient set for fabrication rather than a literal measurement of one transistor dimension. When comparing factories or processes, examine the full set of capabilities:
| Comparison axis | Questions to ask |
|---|---|
| Feature size and layer criticality | Which layers require the tightest dimensions and overlay? |
| EUV/DUV capability | Which exposure technologies are available, and for which layers? |
| Wafer diameter | Does the site run 300 mm, 200 mm, 150 mm or more than one format? |
| Process maturity | Is the recipe new, ramping or proven in high-volume production? |
| Defect density and yield | How many usable dies result for this specific product and die size? |
| Throughput | How many wafers per hour can the bottleneck tools process? |
| Packaging | Can the operation provide the substrate, interconnect and thermal design the chip needs? |
| Business model | Is the site an IDM facility, a customer foundry or part of a fabless supply chain? |
A fab optimized for automotive power devices may be excellent at reliability and mature-node production while lacking the tools needed for leading-edge logic. That is specialization, not a failure to compete.
How a wafer becomes many chips economically
Parallel processing is the central economic idea. Hundreds or thousands of dies share each deposition, exposure, etch and inspection operation. The cost of a wafer therefore spreads across all usable dies rather than being paid separately for each chip. The number of dies per wafer depends on die dimensions, edge exclusion and the wafer diameter.
The economic calculation is completed only after yield and packaging are included. A wafer with 1,000 potential die locations does not produce 1,000 products if defects disable 8 percent, edge locations are incomplete and final test rejects additional parts. Conversely, a mature process with a smaller wafer can be competitive when its tools are fully depreciated and its yield is high.
Industry scale illustrates the volume involved. ASML reported 1.15 trillion semiconductor units shipped in 2021, roughly 145 chips per person based on the world population used in that comparison. The figure includes many types of semiconductors, from simple controllers to advanced processors, rather than one uniform fab product.
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A practical mental model for following one layer
- Start with a clean wafer: the surface is flat, chemically prepared and aligned to the tool’s marks.
- Add material: deposit the conductor, insulator or semiconductor needed for this layer.
- Coat and expose: spin photoresist, align the wafer and project the reticle image.
- Develop: remove selected resist regions to reveal the areas that must change.
- Transfer: etch the exposed film or implant dopants through the openings.
- Strip and clean: remove temporary resist and contamination.
- Measure: verify dimensions, thickness, overlay and defects.
- Feed back: adjust recipes or hold affected wafers before repeating the cycle on the next layer.
Repeating this model explains why a chip is a vertical construction. Lithography defines where a change belongs; deposition, etch and implantation provide the physical and electrical change; metrology confirms that the layer is ready to support the next one.
Common misconceptions to avoid
- “The chip is printed once.” It is patterned layer by layer, often dozens of times.
- “A wafer is one chip.” A wafer is a shared substrate carrying many die copies.
- “The smallest node is always best for every product.” Mature processes can be better suited to analog, power, sensors, automotive and other requirements.
- “A bigger wafer guarantees lower cost.” Usable output depends on die size, defect density, equipment and yield.
- “Yield is a fixed property of a factory.” It changes with product, process maturity, die area and current conditions.
- “Packaging is just a box.” Package interconnect and heat removal affect electrical performance and reliability.
The complete picture
A semiconductor fab turns purified single-crystal silicon into working electronics through a controlled loop of film deposition, resist patterning, lithography, development, etch, implantation, cleaning and measurement. Clean air, stable tools and constant statistical feedback keep nanometer-scale errors from multiplying across a wafer. Front-end processing creates the circuit; back-end assembly and test turn each good die into a reliable component.
The practical outcome is governed by more than feature size. Wafer format, exposure technology, process maturity, defect density, throughput, yield and packaging capability all determine how effectively a fab can convert designs into products. Once those relationships are clear, terms such as wafer, lithography, node, foundry and yield describe specific parts of one connected manufacturing system rather than isolated jargon.
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