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Photonic fabric memory pooling moves part of an AI system’s memory out of individual GPU packages and turns it into a shared tier that several accelerators and servers can use. In Marvell’s 2026 architecture, optical links connect memory modules containing DDR5 and an HBM cache to multiple hosts, with a stated target of up to 32 TB of warm LLM KV-cache capacity at appliance scale. That 32 TB is not HBM inside one GPU or one DIMM; it is a pool available to a group of hosts, potentially across racks. Local HBM still handles the most latency-sensitive work, while the optical tier holds larger, reusable state such as long-context KV caches.

What is photonic fabric memory pooling?

Photonic fabric memory pooling is a disaggregated-memory design: memory is separated from a GPU server and attached to an optical interconnect instead. Hosts, GPUs or other XPUs issue memory transactions to shared modules across that fabric. Capacity can therefore grow independently of compute, so an operator does not have to buy a matching amount of expensive high-bandwidth memory every time more model state is needed.

Marvell describes the approach as making memory shared infrastructure that can be allocated where workloads require it. The company’s 2026 newsroom announcement summarizes the motivation as: “As AI scales, memory must scale more independently of compute.” Those are vendor descriptions of the architecture, not an independent performance result.

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What is inside a Photonic Fabric Memory Module?

A module combines three elements:

  • DDR5 capacity: up to eight DDR5 DIMMs provide the large, comparatively economical capacity tier.
  • HBM cache: 72 GB of HBM is placed in front of the DDR5 to cache frequently accessed data.
  • Optical I/O: 7.2 Tbps of optical-fabric bandwidth carries memory traffic between the module and connected hosts.

Photonic Fabric NICs and chiplets provide the host-side and module-side connectivity. Optical signaling avoids the distance and power penalties that become difficult to manage with long electrical traces, allowing Marvell to describe reach of up to 50 meters.

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How does the optical memory hierarchy serve a GPU?

The design adds a shared tier; it does not remove the accelerator’s own memory. A typical access path is:

  1. Use local HBM first. Model weights, activations and other hot tensors remain in the HBM physically attached to the GPU because it has the shortest path and highest bandwidth.
  2. Check the module’s HBM cache. Frequently reused lines in the pooled tier can be served from the 72 GB cache rather than from DDR5.
  3. Read or write pooled DDR5. Larger, less frequently touched state resides in the module’s DDR5 DIMMs.
  4. Cross the optical fabric when necessary. A Photonic Fabric NIC or chiplet transports the transaction to a module in the same server or elsewhere in the fabric.
  5. Return data to the requesting XPU. Software and the memory protocol must keep placement and coherence rules consistent with the host’s address space.

Marvell’s architecture description targets approximately less than 350 nanoseconds of near-NUMA access across multiple racks. “Near-NUMA” means remote memory is intended to behave more like a second locality domain than a conventional storage request; it is still slower than local HBM, and the quoted value is a vendor architectural target rather than an independently measured production benchmark.

What does 32 TB mean for an AI server or rack?

The headline number is an appliance-level target: up to 32 TB of warm KV-cache offload, according to Marvell’s 2026 announcement. It is shared capacity for a set of XPUs or GPU servers, not 32 TB of HBM in one GPU, not the capacity of one memory module and not automatically 32 TB available to every workload at full speed.

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A related photonic-CXL paper describes a 32 TB configuration spread across 16 hosts using a passive-fiber shuffle and a switch-free crossbar. That example illustrates the scaling model: the aggregate pool is assembled from many hosts and modules. Actual usable capacity depends on the number of modules, reserved space, cache policy, metadata and how the deployment partitions tenants or jobs.

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Why the distinction matters

  • Capacity accounting: a purchasing specification must state the total appliance pool and the per-host allocation; “32 TB” alone does not identify either one.
  • Bandwidth contention: several GPUs can draw from the same optical links, so aggregate throughput and per-tenant guarantees matter as much as raw capacity.
  • Failure domains: a module, NIC, optical path or host failure can remove part of the pool unless the software keeps replicas or rebuilds state.
  • Placement: keeping hot data local to a module or host can avoid unnecessary fabric hops even when the address space is shared.

Does photonic pooled memory replace HBM?

No. Local HBM remains the fastest tier and is still required for the working set that must be accessed at accelerator speed. Photonic memory is a capacity and locality extension: it supplies more bytes at a lower cost and power profile than adding equivalent HBM, while accepting higher latency.

Tier Typical role Relative locality What the cited design establishes
GPU-attached HBM Hot weights, activations and immediate kernel data Closest to the accelerator Remains the fastest tier; no capacity figure is given for a particular GPU.
Module HBM cache Frequently reused lines from pooled memory Near the shared module 72 GB per Photonic Fabric Memory Module.
Module DDR5 Large, warm model state and KV cache Remote or near-NUMA Up to eight DIMMs per module; DIMM capacity is configuration-dependent.
Conventional storage Cold checkpoints, spill files and durable data Farthest and slowest Not replaced by the photonic tier; storage trips can be avoided for data that stays warm.

Why is the LLM KV cache the first target?

During autoregressive generation, a model stores key and value tensors for previous tokens. That KV cache grows with context length, conversation history and the number of concurrent sequences. Long-context and agentic applications can therefore run out of GPU memory even when the model weights fit.

Keeping the cache in a warm shared tier lets another GPU continue a session without reconstructing every prior token or fetching state from storage. The practical benefit is workload-dependent: cache hits, access locality, sequence length, batching and eviction policy determine whether the optical path saves more time than it adds in latency. The architecture is aimed at reducing recomputation and storage traffic, not at making every memory access as fast as local HBM.

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Can pooling make long-context inference cheaper?

It can reduce the amount of HBM that must be provisioned per GPU and increase reuse of a cache across a fleet, which may improve utilization. Marvell claims up to 2–3× higher token throughput within the same data-center footprint and power envelope. That figure is a vendor target for its system; no independent appliance benchmark, production-customer result or public pricing is established in the cited material.

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Cost savings are therefore a capacity-planning question rather than a guaranteed per-request reduction. An operator must compare the price of pooled modules, optical NICs, fabric power and software integration with the HBM and GPU servers that would otherwise be purchased, then measure hit rates and tail latency on its own models.

How does photonic pooling compare with CXL and Ethernet/RDMA memory?

All three approaches separate some memory from the accelerator, but they differ in transport, latency goals and deployment maturity. The values below are the figures or qualifications publicly stated for the cited designs; a “not stated” cell means no comparable number was supplied.

Attribute Photonic fabric pooling CXL memory expansion Ethernet/RDMA pooling
Pooled capacity example Up to 32 TB warm KV-cache appliance target; a related paper models 32 TB across 16 hosts. Enfabrica EMFASYS advertises up to 18 TB of CXL DDR5 per system, expandable to 28 TB. Depends on the server, memory appliance and network; no single capacity is established.
Memory-access latency Approximately less than 350 ns near-NUMA across multiple racks, according to Marvell. Not stated for the cited EMFASYS configuration. Usually includes a network and software path; a directly comparable figure is not stated.
Bandwidth Up to 7.2 Tbps optical-fabric bandwidth per module. Defined by the CXL generation and link width; no value is stated for the cited system. EMFASYS uses 400G/800G RDMA Ethernet.
Reach Marvell describes up to 50 meters and multi-rack operation. Normally constrained by the CXL link and chassis design; rack-to-rack reach is not stated. Ethernet can span racks and data-center fabrics, subject to network design.
Power per transferred byte Marvell argues optical links reduce the reach and power penalties of long electrical paths; no independent joules-per-byte figure is given. Not stated. Not stated; switches and network interfaces add their own power.
Protocol and software compatibility Requires Photonic Fabric NICs/chiplets and software that understands the shared tier. Uses the CXL memory protocol, with host and operating-system support required. Uses RDMA/Ethernet semantics; applications generally need a memory service or distributed-runtime integration.
Sharing an LLM KV cache across hosts Explicit design target for warm shared KV cache. Possible when software exposes shared memory, but not established by the cited capacity figure. Possible through a distributed cache service; access is not the same as coherent shared memory.
Deployment maturity Architecture and vendor targets are public; final shipping configuration and production scale remain open. Commercial systems exist, including the cited EMFASYS offering. RDMA networking is established, but memory-pooling behavior varies by implementation.

What hardware and software does a deployment require?

A practical installation needs more than optical cables. Plan for the following components and controls:

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  • Compatible host adapters: Photonic Fabric NICs or chiplets must be supported by the selected GPU servers and PCIe or package interface.
  • Memory modules: Populate DDR5 DIMMs and the module HBM cache according to the capacity and cache policy required.
  • Optical fabric layout: Keep links within the stated reach and engineer redundant paths if a single cable or module cannot be a failure point.
  • Addressing and placement: Define which NUMA domains can access which pool segments and reserve local HBM for latency-critical kernels.
  • KV-cache policy: Set admission, eviction, sharing and isolation rules so one tenant cannot consume the warm tier needed by another.
  • Observability: Measure hit rate, remote-read latency, fabric utilization, queue depth and token throughput; aggregate capacity alone does not reveal contention.

For comparison, Enfabrica’s EMFASYS advertises up to 18 TB of CXL DDR5 per system, expandable to 28 TB, over 400G/800G RDMA Ethernet. That is a different transport and product architecture, so its capacity should not be added to or treated as an equivalent of Marvell’s 32 TB target.

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What performance claims are established, and what is still unknown?

The cited materials establish the module composition, optical-fabric role, 50-meter reach claim, near-NUMA latency target, warm-KV-cache use case and vendor throughput targets. They do not establish public pricing, named production customers, an independently measured appliance throughput, a final shipping configuration or reseller terms.

Columbia University researchers reported simulated improvements of 5.4×–7.5× in deep-learning training and inference time for a photonic pooling architecture in 2025. Those are simulation results, not measurements of a Marvell appliance. Keeping that distinction clear prevents a modeled upper bound from being mistaken for a deployed-system guarantee.

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When should an AI infrastructure team consider pooled photonic memory?

Start with workload evidence, not the 32 TB headline. Pooling is most relevant when GPU HBM is repeatedly exhausted by warm state, when sessions migrate between hosts, or when recomputing long contexts costs more than a remote memory read.

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A useful qualification checklist

  • Measure the peak and average KV-cache bytes per request and the percentage of cache accesses that can be served without recomputation.
  • Separate hot tensors that must remain in local HBM from warm state that tolerates near-NUMA latency.
  • Model concurrency and worst-case fabric contention, not just a single-stream benchmark.
  • Compare total cost of ownership with additional HBM-equipped servers, including optical modules, NICs, power, cooling and software work.
  • Require an acceptance test for p50 and p99 remote-read latency, token throughput, failover behavior and tenant isolation.

If the workload has little reusable state, short contexts or strict microsecond-level latency requirements, extra local HBM may be simpler. If many GPUs hold mostly idle cache capacity while other hosts page or recompute, a shared tier can improve utilization by allowing capacity to follow demand.

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What should buyers verify before ordering?

Ask the supplier to specify whether the quoted capacity is raw or usable, how much is reserved for metadata and cache tags, and how capacity is divided among hosts. Request the exact DIMM population, HBM-cache size, optical topology, supported host interfaces, software stack, replacement procedure and measured performance under multi-tenant load.

Because final shipping details, pricing and independent benchmarks are not public in the cited announcements, treat current figures as architecture targets until a configuration-specific statement of work and acceptance test are available.

Frequently Asked Questions

Can one GPU address all 32 TB directly?

Not automatically. The 32 TB figure describes an appliance-level shared tier, and software must define address mapping, permissions and placement across hosts; a single GPU’s local address space and operating-system support determine what it can actually access.

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What happens to a KV cache when a pooled-memory module fails?

The cache is normally recoverable state rather than the model’s only durable copy, but the application still needs an eviction or rebuild policy. Ask for the vendor’s redundancy, health-monitoring and failover behavior because those details are not specified by the capacity headline.

Is optical pooled memory useful for model training as well as inference?

It can hold larger datasets or optimizer state, and a 2025 Columbia simulation explored both training and inference. Training benefits will depend on synchronization patterns and whether remote accesses overlap with computation; the simulation is not a production benchmark.

How is pooled memory isolated between customers or teams?

Isolation requires hardware access controls plus software quotas and scheduling. A deployment should document tenant-level capacity limits, address protection, encryption requirements and what telemetry administrators can see before placing multiple workloads on one pool.

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