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Google Willow and IBM Heron are both superconducting quantum processors, but they are intended to prove different things. Willow’s headline result is a below-threshold surface-code experiment in which enlarging the code reduced the logical error rate. Heron is a processor family focused on low physical-gate errors, tunable couplers, signal delivery, and integration into IBM’s modular System Two and cloud platform. Willow has 105 physical qubits; the documented Heron r2 generation has 156. Neither count, by itself, identifies a universal winner.
Willow and Heron at a glance
The most useful comparison separates three layers that are often mixed together: the number of physical qubits on the chip, the quality of individual operations, and the progress toward a logical qubit that actively corrects errors. Willow’s public milestone is primarily at the third layer. Heron’s published specifications and product positioning are primarily at the first two layers and at system integration.
| Characteristic | Google Willow | IBM Heron |
|---|---|---|
| Processor status | Single 105-qubit superconducting processor announced December 9, 2024 | Processor family; IBM documents a 133-qubit r1 generation and a 156-qubit r2 generation |
| Public headline | Below-threshold surface-code error-correction experiment | High-performance physical processor and building block for modular System Two |
| Qubit count cited here | 105 physical qubits | 156 physical qubits in documented r2; 133 in r1 |
| Published error figure | Mean simultaneous single-qubit gate error of 0.035% ± 0.029% on the specification sheet | Best two-qubit gate error of 8 × 10−4, measured by randomized benchmarking |
| Control and connectivity emphasis | Surface-code lattice with integrated control and readout performance | Fixed-frequency superconducting qubits, tunable couplers, and signal-delivery improvements |
| Scaling path described publicly | Increase surface-code size and lower logical error rates | Combine processors in System Two and expose them through IBM’s cloud-accessible fleet |
IBM’s processor documentation describes the Heron family and its generations at IBM Quantum’s processor guide. Google’s explanation of Willow’s error-correction result appears in Google Research’s Willow announcement.
What Willow is designed to demonstrate
A 105-qubit chip built around a logical-qubit milestone
Google announced Willow on December 9, 2024, as a 105-qubit superconducting processor. The chip matters less because 105 is a large integer than because Google used it to test whether a surface-code error-correction architecture improves as it grows. In a fault-tolerant design, many noisy physical qubits are combined to represent a smaller logical qubit. The central engineering question is whether adding the next layer of physical qubits suppresses errors faster than it introduces new opportunities for failure.
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Google reports that Willow crossed the relevant surface-code threshold in its experiment: when the code was scaled to larger sizes, the logical error rate went down rather than up. That direction of change is the crucial result. A processor can have excellent individual gates and still be unable to produce a useful logical qubit if error correction gets worse at larger code sizes.
What “below threshold” means
The surface-code threshold is not a single marketing score for a chip. It is a boundary in an error-correction scheme. Below the threshold, the effective physical error rates are low enough, and the operations are controlled well enough, that increasing the code distance can reduce the probability that an encoded logical operation fails. Above the threshold, adding more physical qubits to the same code does not deliver that benefit.
Willow’s result therefore demonstrates a scaling trend, not a finished fault-tolerant computer. The announcement calls the system a prototype for a scalable logical qubit. It does not mean that Willow can run arbitrary long algorithms without error, nor that the chip has converted all 105 physical qubits into one production-ready logical qubit.
Willow’s other published performance information
Google also reports random-circuit-sampling performance for Willow. That benchmark indicates how quickly a particular processor can generate samples from a deliberately difficult circuit, but it is not the same measurement as the surface-code logical-error experiment. The Willow specification sheet lists a mean simultaneous single-qubit gate error of 0.035% ± 0.029%. The figure is a processor specification, while the below-threshold claim concerns how encoded errors change as the surface-code size increases.
What Heron is designed to demonstrate
A family rather than one fixed chip
“Heron” refers to a family of IBM processors. IBM’s documentation lists an earlier 133-qubit r1 generation and a 156-qubit r2 generation. When someone asks whether Heron has more qubits than Willow, the precise answer is yes for the documented r2 generation: 156 versus 105. The comparison must identify the Heron revision, because the family includes more than one generation.
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IBM describes Heron as an Eagle-sized upgrade to Egret that incorporates signal-delivery innovations previously deployed in Osprey. The emphasis is on making a high-performance processor that can operate as part of a larger service, not solely on demonstrating one surface-code scaling curve.
Fixed-frequency qubits and tunable couplers
IBM’s public hardware approach uses fixed-frequency superconducting qubits connected through tunable couplers. A coupler is the controllable interaction element that lets neighboring qubits exchange information for two-qubit operations while reducing unwanted interactions when that connection is not being used. IBM highlights this coupling arrangement alongside improvements in how control signals are delivered to the chip.
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Those design choices target the physical layer: reliable two-qubit operations, manageable crosstalk, and control electronics that can support a larger processor. They are important ingredients for error correction, but they are not themselves a claim that Heron has achieved Willow’s below-threshold surface-code result.
Heron’s published two-qubit metric
IBM’s 2024 annual research letter reports a best two-qubit gate error rate of 8 × 10−4 for its 156-qubit Heron chip, measured using randomized benchmarking. That is a physical-operation metric. Randomized benchmarking estimates how errors accumulate in a selected family of gates under a defined test protocol; it does not directly report the logical error rate of a surface-code qubit.
The distinction matters when reading headlines. A low two-qubit gate error can make an error-correcting architecture more practical, but it cannot be converted directly into a Willow-style logical-error result without knowing the code, decoder, measurement cycle, connectivity, leakage behavior, and other system details.
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Why the qubit count does not decide which chip is better
Physical qubits are the raw devices on a chip. Logical qubits use groups of physical qubits plus repeated measurements and classical decoding to protect quantum information. The overhead can be substantial, so a chip with more physical qubits may still produce fewer logical qubits—or none that meet a target error rate—than a smaller chip with better operating margins.
- More physical qubits can increase capacity: a larger array may provide room for more encoded qubits, more routing options, or larger error-correcting codes.
- More qubits also create more failure opportunities: every additional qubit, coupling element, measurement channel, and control path must remain within the architecture’s error budget.
- Connectivity changes the overhead: the physical layout determines how many operations are needed to move information or perform stabilizer checks.
- Calibration and control matter: a nominal qubit count says nothing about how uniformly the devices perform across the chip or how stable that performance remains.
For that reason, “Heron has 156 qubits, so it beats Willow” is not a valid conclusion. The two processors publish different kinds of evidence about different objectives.
The error numbers answer different questions
| Metric | Willow figure | Heron figure | What it tells you |
|---|---|---|---|
| Single-qubit gate error | 0.035% ± 0.029% mean simultaneous error, from Google’s 2024 specification sheet | Not stated in the cited Heron material | How accurately one-qubit operations perform under the stated simultaneous-gate measurement |
| Two-qubit gate error | Not stated in the cited Willow material | 8 × 10−4 best value for the 156-qubit chip, measured by randomized benchmarking in IBM’s 2024 annual research letter | How accurately selected two-qubit operations perform under IBM’s benchmarking protocol |
| Logical error scaling | Google reports that increasing the surface-code size reduced the logical error rate | No equivalent below-threshold Heron result is stated in the cited material | Whether the error-correction architecture improves as its code grows |
| Random-circuit sampling | Reported by Google for Willow | Not stated in the cited material | Performance on a specific sampling benchmark, not a universal application score |
Because the tests use different units, protocols, and targets, there is no honest single ranking that combines 0.035%, 8 × 10−4, and a below-threshold trend. A reader comparing processors should first ask whether the goal is a physical gate, an encoded logical operation, a sampling benchmark, or access to a larger modular system.
Is Willow’s error correction different from IBM’s approach?
Willow: prove that scaling the code helps
Willow’s public result centers on a surface-code lattice. Google varied the code size and observed a falling logical error rate, which is the behavior required for a scalable error-correction path. The claim is architectural: the processor and its control stack operated well enough for the encoded system to move below threshold.
Heron: improve the physical processor and system around it
Heron’s cited public description emphasizes tunable couplers, signal delivery, physical gate performance, and modular integration. These are enabling technologies for fault-tolerant operation, but the cited Heron material does not report the same surface-code scaling experiment or a corresponding below-threshold logical-error curve.
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That does not establish that IBM has no error-correction work. It establishes only that the published Heron figures used here support a different comparison. Willow supplies direct evidence about one error-correction milestone; Heron supplies direct evidence about physical processor performance and the path to a modular system.
How the two scaling paths differ
Google’s code-first scaling path
- Arrange physical qubits in the surface-code layout.
- Run repeated checks that detect error syndromes without directly measuring the protected quantum information.
- Decode those check results to infer and correct likely errors.
- Increase the code size and verify that the logical error rate decreases.
The important output is not simply a larger chip. It is evidence that additional physical resources buy a more reliable encoded qubit. Google describes Willow’s below-threshold behavior as the strongest prototype in its program to date for a scalable logical qubit.
IBM’s processor-and-module scaling path
- Improve the physical processor’s two-qubit operations and signal delivery.
- Use tunable couplers to control interactions between fixed-frequency qubits.
- Integrate Heron processors into System Two’s modular architecture.
- Expose processors through IBM’s cloud-accessible fleet and software stack.
This path treats the processor as one module in a broader system. Its success depends on the quality of each chip and on the links, controls, scheduling, calibration, and software that let multiple modules work together. The Heron documentation positions the family as a foundation for that system approach.
Which processor is better for a particular goal?
| If your priority is… | The better-supported fit | Why |
|---|---|---|
| Studying whether a surface-code experiment is below threshold | Willow | Google reports the defining result: logical error rate decreased as code size increased. |
| Comparing the largest cited physical-qubit count | Heron r2 | The documented r2 generation has 156 physical qubits versus Willow’s 105. |
| Evaluating a published two-qubit gate benchmark | Heron | IBM reports a best 8 × 10−4 two-qubit error rate from randomized benchmarking. |
| Evaluating the cited simultaneous single-qubit specification | Willow | Google lists a 0.035% ± 0.029% mean simultaneous single-qubit gate error. |
| Following a modular hardware and cloud-access strategy | Heron | IBM positions Heron inside System Two and its cloud-accessible processor fleet. |
| Choosing a universal winner for an unspecified application | Neither can be declared | The published measurements target different layers and do not establish workload-specific application performance. |
If you are selecting a processor for a real algorithm, define the workload before comparing chips. A circuit dominated by two-qubit interactions may be more sensitive to Heron’s reported two-qubit benchmark. An investigation of logical protection may care more about Willow’s surface-code scaling. A cloud experiment may depend on which processor revision, queue, software interface, and system configuration is actually available at the time of use.
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Check the generation and date
Use “Heron r2” when referring to the 156-qubit figure, and keep Willow’s December 9, 2024 announcement date attached to its 105-qubit specification. Processor families change; a family name without a revision can conceal a different qubit count or calibration result.
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Keep physical and logical metrics separate
Write down whether each number describes a physical gate, an encoded operation, a sampling task, or a system-level throughput measurement. Do not place values from those categories in one league table as though they were interchangeable.
Ask what was measured simultaneously
Google’s 0.035% ± 0.029% figure is a mean simultaneous single-qubit gate error. IBM’s 8 × 10−4 figure is a best two-qubit result from randomized benchmarking. “Mean” versus “best,” single-qubit versus two-qubit, and simultaneous operation versus benchmarking protocol each change the interpretation.
Look for a scaling curve, not only a peak specification
A peak gate number shows what the best-performing operation achieved under a stated test. A scaling curve shows whether the architecture continues to improve as more resources are added. Willow’s public distinction is the latter; Heron’s cited distinction is the former plus modular-system integration.
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What neither result proves
- Willow is not presented as a general-purpose, fully fault-tolerant quantum computer.
- Heron’s larger physical-qubit count does not prove a lower logical error rate or better application performance.
- The Willow and Heron error percentages cannot be converted into one common score without equivalent test definitions.
- A below-threshold experiment does not remove the engineering work needed for larger codes, more logical qubits, fault-tolerant gates, decoding, and system control.
- A strong physical-gate benchmark does not by itself demonstrate that an entire logical architecture is below threshold.
Access and practical use
Heron processors are documented as part of IBM’s cloud-accessible platform, so users who want to run circuits should check the current IBM Quantum service documentation for which Heron revision and execution options are available to their account. Availability, queue behavior, calibration data, and software support can change independently of the chip’s headline specifications.
Willow’s published announcement is primarily a hardware and error-correction result. The material cited here does not establish a general public programming route to a Willow chip, so it would be incorrect to assume that the 105-qubit processor is available on demand in the same way as a cloud fleet.
Bottom line: different approaches, not a single winner
Willow and Heron represent two complementary priorities in superconducting quantum engineering. Willow’s strongest public evidence is that a surface-code experiment became more reliable as the code grew, a necessary condition for scalable logical qubits. Heron’s strongest public evidence is a 156-qubit r2 processor with a reported best two-qubit gate error of 8 × 10−4, tunable-coupler and signal-delivery improvements, and a role in IBM’s modular System Two strategy.
Choose Willow when the question is whether an error-correcting code is beginning to suppress logical errors. Choose Heron when the question concerns the documented physical-qubit count, the cited two-qubit gate benchmark, or IBM’s modular and cloud integration. For any specific algorithm, the responsible answer remains workload-dependent because the two platforms publish different measurements rather than a common application benchmark.
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