The Tool Desk
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Short answer: EUV and DUV are complementary wafer-patterning technologies, not competing labels for an entire chip. Advanced DUV uses 193 nm argon-fluoride (ArF) light (and, for less demanding layers, 248 nm krypton-fluoride light); EUV uses 13.5 nm light. EUV’s shorter wavelength can print the tightest layers with fewer patterning cycles, while DUV still prints many other layers on the same advanced logic or memory device. That division matters for AI hardware because manufacturing cost, overlay accuracy, power use and yield depend on the complete sequence of exposures, masks, etch steps and deposition—not on a single scanner’s wavelength.
This guide separates wavelength, optical resolution, process-node names and equipment specifications, then shows where each technology fits in AI-oriented logic and memory production.
At a glance
| Name | Best for | Key spec | Checked |
|---|---|---|---|
| DUV lithography | Most chip layers, including advanced layers made with immersion and multi-patterning | 193 nm ArF for leading DUV; 248 nm KrF also used; refractive lenses, with water immersion in the most advanced systems | Oct 2026 |
| EUV lithography | The most intricate layers on some leading-edge logic and memory devices | 13.5 nm light; multilayer mirrors in vacuum; laser-produced tin plasma source | Oct 2026 |
What is the difference between EUV and DUV lithography?
DUV and EUV differ primarily in the wavelength used to project a mask pattern onto a photoresist-coated wafer. ASML identifies 193 nm ArF and 248 nm KrF as DUV wavelengths, while EUV systems use 13.5 nm light (ASML’s lithography overview). The wavelength is a property of the exposure light; it is not a process-node number.
The shorter EUV wavelength gives the imaging system more room to resolve small features, but wavelength alone does not determine the printed dimension. ASML expresses the Rayleigh relationship as CD = k1 × wavelength / NA, where CD is critical dimension, NA is numerical aperture and k1 captures process-dependent effects such as illumination, mask design and resist processing (ASML’s Rayleigh-criterion explanation). A lower wavelength helps, while a larger NA and a well-optimized process can also improve resolution.
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What “critical dimension” means
Critical dimension is the measured width of a printed feature that matters to the circuit, such as a line, space or contact opening. It is a manufactured feature size, not automatically equal to the marketing name of a process. A “3 nm” node therefore does not mean the tool uses 3 nm light or that every line on the wafer is 3 nm wide.
Why node names and wavelengths must stay separate
Foundries use node labels to identify a generation of process technology. The label can bundle transistor architecture, density, performance and design rules, and does not provide a literal wavelength or a promise about every physical feature. To understand a process claim, ask separately which wavelength is used, what NA the scanner has, which layers are EUV or DUV, and what dimensions the manufacturer actually specifies.
How does a DUV scanner print a wafer?
DUV scanners use refractive lenses to reduce and project a reticle pattern onto the wafer. Excimer lasers generate the ArF or KrF illumination, and the projection optics focus it through the lens system. For advanced DUV, immersion puts a thin layer of water between the final lens element and the wafer. The water increases the effective numerical aperture, helping the system print smaller features than a dry lens at the same wavelength.
DUV’s mature ecosystem is a major reason it remains present on advanced products. The same family of tools can cover many critical and non-critical layers, and fabs can combine immersion DUV with different resist, etch and deposition recipes. Less demanding layers do not benefit enough from EUV to justify changing the entire process around them.
Why DUV often uses multi-patterning
When one 193 nm exposure cannot resolve a dense pattern with acceptable pitch and line-edge control, engineers can split the layout into two or more masks. Each mask is exposed and developed in a separate cycle, with intervening deposition, etch, spacer or clean steps. This multi-patterning route lets DUV build a final structure from simpler images, but every additional cycle adds alignment opportunities, process time, masks and yield risk.
Multi-patterning is not a single standardized recipe. The number of exposures and the exact decomposition depend on the layer, design rules, resist and etch integration. It is therefore inaccurate to describe all DUV layers as multi-patterned or to assume that a particular node always needs the same number of exposures.
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How does EUV work differently?
EUV at 13.5 nm is absorbed by air and by ordinary optical materials, so an EUV scanner cannot use the transmissive lenses found in DUV tools. Instead, it guides the light with multilayer reflective mirrors inside a vacuum chamber (ASML explains the light and optical path). Every mirror’s coating and surface quality affect how much of the already scarce EUV radiation reaches the wafer.
Laser-produced tin plasma creates the light
An EUV source fires laser pulses at tiny tin droplets. The laser turns each droplet into a hot plasma that emits EUV radiation; collection optics then direct the usable light toward the projection system. This source architecture is fundamentally different from the excimer lasers used for ArF and KrF DUV.
Numerical aperture still matters
EUV’s wavelength advantage does not remove the need for optical engineering. ASML lists a 0.33 NA for its NXE EUV platform and a 0.55 NA for High-NA EXE systems. The company describes approximately 13 nm and 8 nm tool resolutions for those platforms respectively on its EUV product information (ASML EUV systems). Those are scanner-resolution specifications, not node names and not a statement that every printed feature has that dimension.
Why can one chip use both EUV and DUV?
A modern chip contains layers with very different patterning difficulty. The most crowded interconnect, contact or transistor layers may benefit from EUV, while power, isolation, alignment and other layers can be printed economically with DUV. ASML describes the division plainly: “EUV systems are used to print the most intricate layers on a chip, with the rest of the layers printed using various DUV systems” (ASML EUV systems).
This mixed strategy avoids paying the EUV complexity penalty where its resolution is unnecessary. It also means that asking whether a chip is “EUV” or “DUV” oversimplifies the manufacturing flow. The useful questions are how many layers use each technology, whether a critical layer is single- or multi-patterned, and how the complete sequence affects cost and yield.
Does EUV replace DUV multi-patterning?
EUV can simplify selected critical layers that would otherwise require multiple DUV masks and exposures, but it is not a universal one-exposure guarantee. A layer’s pitch, resist performance, stochastic defects, overlay budget and etch integration determine whether one EUV exposure is sufficient. Some layers can still require additional patterning even when EUV is used.
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What EUV can eliminate
Where a single EUV image meets the layer’s design and process requirements, the fab may avoid some of the mask splits and alignment steps associated with DUV multi-patterning. Fewer patterning cycles can reduce process complexity and the number of opportunities for overlay error. The benefit is strongest on layers whose geometry is too dense for a practical single DUV exposure.
What EUV does not eliminate
EUV still needs a mask, resist coating, develop, etch and inspection. It also has its own defect, dose and stochastic-control challenges. A fab must evaluate the full integration flow rather than count exposures in isolation; a nominally simpler exposure can be offset by source, mask, resist or inspection requirements.
Is EUV cheaper or more efficient than DUV?
There is no universal winner based on scanner purchase price or electrical power alone. DUV multi-patterning can require more masks, exposures and downstream process steps, while an EUV scanner is a highly complex machine that consumes more power than a DUV scanner. ASML cautions that sustainability and cost comparisons require whole-fab assumptions (ASML 2025 annual report).
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A meaningful comparison includes:
- Number and cost of masks for each patterning route.
- Exposure time and wafer throughput for every step, not just the lithography scan.
- Overlay control across repeated exposures.
- Resist, etch, deposition, clean and inspection cycles added by multi-patterning.
- Defectivity, wafer yield and the cost of wafers that meet specifications.
- Tool utilization, maintenance, energy and facility requirements.
For example, ASML’s 2025 annual report gives the NXE:3800E a full-specification throughput of 220 wafers per hour, described as a 37% improvement over the NXE:3600D. That is an equipment specification and an intra-EUV generation comparison, not proof that EUV processes more wafers per hour than DUV or that it has a lower cost per usable wafer.
Can DUV make advanced AI chips?
Yes. DUV remains necessary for many layers of advanced logic and memory, including devices used in AI systems. ASML states that DUV produces the majority of chip layers, while EUV is directed at the most intricate layers (ASML 2025 annual report). A product can therefore contain leading-edge circuitry and still rely extensively on DUV processing.
DUV can also manufacture chips without any EUV when the design rules and density fit the available process. Whether a particular AI processor, accelerator or memory device uses EUV depends on its foundry, process generation, layer dimensions and production economics. The cited equipment descriptions do not establish the lithography flow of every named AI product, so a node label or marketing statement should not be treated as proof of EUV use.
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Where does EUV matter in AI-related logic and memory?
AI hardware increases demand for dense logic, large caches, high-bandwidth memory and advanced packaging. The densest front-end layers in some leading-edge logic processes are candidates for EUV, while other logic layers and the majority of total layers continue to use DUV. The exact split is process-specific.
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Advanced logic
ASML associates its NXE EUV systems with intricate layers at 7 nm, 5 nm and 3 nm process generations (ASML EUV systems). This association describes where the platform is used in industry; it does not mean every product marketed at one of those nodes uses EUV on every critical layer.
DRAM and other memory
Samsung has documented EUV use in DRAM, showing that EUV is relevant beyond logic (Samsung’s EUV lithography explanation). Memory makers still combine lithography technologies across a process, and the cited documentation does not establish a single EUV percentage or exposure count for every DRAM generation.
What does High-NA EUV change?
High-NA EUV increases numerical aperture from the 0.33 NA used by NXE systems to 0.55 NA in ASML’s EXE platform. Because NA appears in the denominator of the Rayleigh relationship, the higher value can improve imaging resolution, subject to the associated optics, depth of focus, mask and process constraints.
ASML’s EUV product page has described High-NA EXE as supporting high-volume manufacturing in 2025–2026, while the company’s 2025 annual report says it expects the EXE platform to start supporting high-volume manufacturing in 2027. The 2027 date is an expectation stated in that report, not confirmation that production has begun (ASML 2025 annual report). High-NA availability therefore should be discussed with its date and source rather than as an established production fact.
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Use this checklist when a vendor, foundry or analyst mentions EUV, DUV or a node:
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- Identify the wavelength. Confirm whether the statement means 193 nm ArF, 248 nm KrF or 13.5 nm EUV.
- Separate the node from the optics. A 3 nm or 5 nm label is not a light wavelength and does not specify every feature size.
- Ask which layers use which tool. “Uses EUV” can mean only a subset of the most intricate layers.
- Check the NA and stated resolution. Treat 0.33 or 0.55 NA and a tool-resolution figure as equipment characteristics, not as node names.
- Look for the patterning strategy. Determine whether DUV multi-patterning or EUV reduces exposures for the specific layer under discussion.
- Evaluate the complete process. Include masks, overlay, etch, deposition, inspection, power, throughput and yield rather than comparing scanner wattage.
- Check the date and geography. Product pages, annual reports and regional manufacturing announcements can describe different schedules or expectations.
What are the practical trade-offs for a fab?
DUV offers established lenses, excimer sources and broad layer coverage, but dense patterns may need repeated exposures and tighter overlay control. EUV offers a much shorter wavelength and can reduce patterning complexity on selected layers, yet it requires reflective optics, a vacuum environment, a tin-plasma source and demanding source and mask control.
The decision is consequently an integration problem. A fab chooses the route that delivers the required critical dimensions and yield at an acceptable cost per usable wafer. The answer can differ by layer, product volume, memory versus logic design and process generation, even within the same facility.
Further reading on lithography fundamentals
Readers who want the underlying optics and process mathematics can consult Chris Mack’s Fundamental Principles of Optical Lithography: The Science of Microfabrication, physical paperback ISBN 978-0-470-72730-0, listed by Wiley (Wiley book information). It is an advanced reference, not equipment required to design or operate an AI chip.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchWhat should you remember about EUV and DUV?
EUV is best understood as a selective resolution tool inside a larger DUV-and-EUV manufacturing flow. Its 13.5 nm wavelength and reflective vacuum optics can simplify some of the tightest layers, while 193 nm immersion DUV, 248 nm DUV and other process steps handle the rest. For AI-chip comparisons, the decisive evidence is the layer-by-layer process and its resulting cost, yield and performance—not the node name by itself.
Frequently Asked Questions
Is EUV light a type of X-ray radiation?
EUV sits at a much shorter wavelength than DUV and is strongly absorbed by air and many materials, which is why the scanner uses a vacuum and mirrors. Calling it simply “X-ray lithography” would blur the source, optics and process distinctions used in semiconductor equipment.
Why does EUV need mirrors instead of lenses?
At 13.5 nm, common lens materials absorb too much light for a practical projection system. Multilayer reflective mirrors preserve the usable beam, but they must be manufactured and aligned to extremely tight surface and coating specifications.
Does using EUV guarantee a smaller transistor or faster AI processor?
No. EUV can enable particular pattern dimensions or reduce patterning steps, but chip speed and efficiency also depend on transistor architecture, interconnects, design, power delivery, packaging and the rest of the process. Lithography wavelength alone cannot predict product performance.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsWhy can a newer DUV tool still be important after a fab adopts EUV?
EUV is economically justified mainly for layers that need its resolution. Newer immersion DUV tools continue to print the many layers where their lenses, throughput and established process control are sufficient, so a fab normally expands both capabilities rather than replacing DUV outright.
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