In an Andes Technology case study published by RISC-V International, targeted RISC-V custom instructions cut reported FIR, LMS, and active-noise-control (ANC) workloads from thousands of cycles to 128–250 cycles. The approach moves hot audio-processing work into specialized datapath logic, allowing the CPU to run at a reported 80 MHz while reducing cycle demand. The figures are typical case-study results—not independently audited measurements—and the authors say they cannot disclose the proprietary chip’s actual final results.
What the earbud chip had to do
The case study concerns a true-wireless-stereo (TWS) earbud system-on-chip built primarily around a Bluetooth RF transceiver. Its audio processing includes a 128-tap finite impulse response (FIR) filter, a 128-tap least-mean-square (LMS) adaptive filter, and a hybrid ANC function. The design also includes an RF baseband controller, 64 kB of exchange memory, two independently operating speakers and microphones, synchronized phase-locked loops, a RISC-V CPU with P DSP/SIMD extensions, a standalone DSP, SRAM, DMA, and AXI/AHB interconnect.
One additional workload comes from moving data between unlike formats: Bluetooth data is 16-bit little-endian, while the audio path is 24-bit big-endian. Converting between them adds computation alongside filtering and noise control.
Why ANC is a demanding workload
In the case study’s ANC example, the 128-tap FIR and LMS filters together require 896 additions and 896 multiplications per sample. The ADC and DAC operate at 192 kHz, or roughly one sample every 5.2 microseconds. That tight, recurring deadline makes the number of operations—and the time each operation takes—important to the design.
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Reported cycle reductions
The case study reports the following typical improvement data. These are workload-cycle figures, not independently validated end-to-end latency, power, or battery-life measurements.
| Workload | Baseline | Custom implementation | Reported improvement |
|---|---|---|---|
| FIR | About 1,600 cycles in the PDF’s pure-C estimate | 128 cycles | 12× speedup, as reported by the case study |
| LMS | 1,820 cycles | 128 cycles | 14× speedup, as reported by the case study |
| ANC | 10,404 cycles | 250 cycles | 40× reduction, as reported by the case study |
The broader RISC-V International summary gives a different FIR baseline: 1,693 cycles rather than the PDF’s approximately 1,600-cycle pure-C estimate. The figures use different workload-accounting scopes; they should not be treated as competing measurements of an identical baseline. The PDF’s quoted FIR comparison uses the pure-C estimate.
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How the custom extensions work
Instead of relying on general-purpose instructions for every operation, the design team added one custom instruction for FIR and one for LMS. For ANC, it developed supporting multiplier, adder, and storage hardware. The case study describes these changes as narrowly targeted at the identified processing hotspots, rather than replacing the whole CPU or audio subsystem.
Andes ACE and CoPilot were used to create and integrate the instructions into the design and verification flow. The tools assigned background attributes that allowed customized instructions to run in parallel. In practical terms, the combination of instruction-level customization and supporting datapath hardware reduced the cycles required by the hot kernels; it also gave the team a way to incorporate the changes into its existing design flow.
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What the results say about PPA
Performance
The clearest reported result is fewer cycles for the selected FIR, LMS, and ANC workloads. This is a kernel-level improvement: it does not establish the speedup for every task in the earbud, or for the complete audio pipeline under all operating conditions.
Power
The case study says the custom logic enabled an 80 MHz CPU clock and reduced power, with the potential to extend battery life. A lower clock can reduce power, but the published material does not provide measured silicon power or battery-life hours. The cycle counts alone cannot establish how much energy the finished product uses.
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Area
The case study says custom logic can use fewer gates and a smaller silicon footprint. It does not report a measured die-area reduction or gate-count comparison for this proprietary design. Custom instructions also require hardware support, so area depends on what is added and what existing implementation can be simplified.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What this case study does—and does not—establish
The PDF explicitly says its authors cannot comment on the proprietary design’s actual final results and presents the table as typical improvement data. The cycle reductions should therefore be read as reported case-study figures, not as independently audited benchmarks or measurements of the shipping chip’s complete PPA.
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The case study further states that the chip taped out successfully without a design spin and is shipping in Razer True Wireless Pro earbuds. That is an Andes Technology vendor case-study claim about a proprietary design; the public material does not disclose underlying product measurements for area, power, or battery life.
How to compare this approach with a commercial reference design
Qualcomm’s QCC3020 product page describes a low-cost, occluded-earbud reference design integrating power management, an audio DSP, an application processor, Bluetooth RF, GPIO, and audio inputs and outputs. It lists a 40 mAh earbud battery and a 280 mAh charger battery as reference-design specifications. Those figures are not measurements of the Andes case-study chip, and they do not provide a like-for-like PPA comparison.
For an engineering or product decision, compare designs using evidence at the same scope. Useful dimensions include:
Quick Recap
- Workload cycles and latency: determine which kernels and complete-path operations were measured, and whether the workloads match.
- Frequency and power: compare clock targets alongside measured power under stated operating conditions; a clock figure by itself is not a power result.
- Gate count or area: establish whether custom datapath logic reduces total implementation cost or adds resources.
- Verification and integration effort: account for the work required to create, integrate, and verify custom instructions.
- Productization status: separate reported reference-design or case-study results from disclosed measurements on a shipping product.
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