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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallSome FPGA soft CPUs are superscalar, but “soft CPU” does not mean “superscalar.” Superscalar capability is a property of an individual processor core: RSD describes itself as an out-of-order superscalar RISC-V core, and a 2026 RVfpga paper describes VeeR EH1 as dual-issue superscalar. Microchip, by contrast, describes its MIV_RV32IMA_L1_AHB core as single-issue and in-order.
What “soft CPU” and “superscalar” mean
A soft CPU is processor logic implemented in programmable FPGA fabric. Unlike a fixed processor in a conventional microcontroller or application processor, its logic is synthesized into the FPGA as part of the design.
A superscalar processor can issue more than one instruction in a clock cycle when the implementation and instruction dependencies allow it. That is a capability, not a promise that every cycle issues multiple instructions or that every workload runs faster.
RISC-V’s specification defines a core in terms of an independent instruction-fetch unit and describes a hardware platform as potentially combining cores with accelerators, physical memories, I/O devices, and interconnect. An FPGA soft CPU is therefore often one element in a larger system rather than the complete system.
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How dual issue differs from out-of-order execution
Issue width, execution order, retirement order, and pipeline depth describe different parts of a processor. “Dual issue” means the core can issue up to two instructions in a cycle under suitable conditions; it does not, by itself, say whether instructions execute or retire in program order.
A 2018 dual-issue RISC-V design described in a reviewed paper illustrates the distinction: it fetches and issues instructions in program order, retires them in order, but can complete execution out of order. So a processor can be dual-issue without being an out-of-order issue machine, and claims about one feature should not be used to infer another.
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Examples of FPGA soft CPUs with different designs
| Core | Documented design | What the description establishes |
|---|---|---|
| RSD | 32-bit RISC-V, out-of-order superscalar processor core | The project repository describes it as an FPGA-optimized soft processor and cites a 2019 IEEE International Conference on Field-Programmable Technology paper by Susumu Mashimo and co-authors. Check the repository’s current build instructions and FPGA targets before selecting it. |
| VeeR EH1 | 32-bit RV32IMC, dual-issue superscalar, nine-stage pipeline | A 2026 RVfpga teaching-package paper reports four ALUs, separate load/store and multiply pipelines, and a 34-cycle out-of-pipeline divider. These are design details reported by the paper, not independent benchmark results. |
| VeeR EL2 | 32-bit RV32IMC, scalar, four-stage pipeline | The same 2026 paper provides a scalar contrast to EH1 within the educational package. |
| Microchip MIV_RV32IMA_L1_AHB | 32-bit RV32IMA, single-issue, in-order | Microchip describes it as based on Rocket-Chip and lists 8 KB instruction and data caches, JTAG debug, and availability with a Libero license. These are vendor-published product details, not an independent evaluation. |
The examples show why the answer to “Are FPGA soft CPUs superscalar?” is core-specific. Even cores in the same broad category—or in the same educational package—can have different issue widths and pipeline organizations.
Does a superscalar soft CPU run faster?
Not necessarily. A wider issue capability can help only when the core has independent instructions to issue and the rest of the implementation can keep them supplied. Clock frequency, dependencies, memory behavior, synthesis results, and workload all affect end-to-end performance.
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The cited sources establish architectural examples and FPGA implementation considerations, but do not provide a controlled, same-device comparison of the listed cores. They therefore do not establish a universal speedup, or an apples-to-apples speed, area, or power ranking. Compare candidate cores on the same FPGA using the same workload, while recording achieved clock rate, throughput, and logic and memory resource use.
What to check when choosing a core or FPGA board
Do not choose by issue width alone. A core’s usable behavior depends on its ISA extensions, execution environment, memory system, peripherals, and integration. The RISC-V specification describes the execution environment as defining such details as initial state, harts, privilege modes, memory and I/O, and interrupt and exception behavior.
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- Architecture: Confirm issue width, whether scheduling and retirement are in order or out of order, pipeline organization, supported ISA and extensions, and cache or memory arrangement.
- System support: Check interrupt and debug support, required peripherals and interconnect, and whether the intended software and toolchain work with the core.
- FPGA fit: Verify the FPGA family, device capacity, on-chip memory and other resource needs, and whether a maintained target configuration exists for the core.
- Measured implementation: Compare synthesis resource use, achieved frequency, and workload performance on the same target rather than treating issue width as a performance result.
- Tool and license requirements: Confirm current FPGA tool support and any vendor licensing requirements before committing to a board or core.
RVfpga documents VeeR-based system deployments on Basys3, Boolean, and Nexys A7 boards. That demonstrates physical deployments for those systems; it does not prove that every core in the comparison supports every board. Current board availability, core targets, toolchains, and licensing can change, so check the relevant project and vendor documentation for the exact combination you plan to use.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why FPGA soft CPUs are useful beyond running software
RISC-V SoftCPU SIG’s charter characterizes FPGA implementations as a platform for processor and system innovation, including memory systems, interconnects, accelerator integration, partial reconfiguration, and the FPGA-specific costs of instruction extensions. Its background states: “RISC-V soft processors are an agile platform for rapid innovation in processor and system architecture and implementation.” This is the working group’s rationale, not a measured performance claim.
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