Applied Materials is investing in equipment and process technologies for two related challenges in advanced chips: patterning ever-smaller features with extreme ultraviolet (EUV) lithography, and building gate-all-around (GAA) transistors with tightly controlled three-dimensional structures. Its tools address pattern transfer, materials deposition and removal, and measurement; they are not a substitute for the full set of processes needed to manufacture a chip.
Why Applied Materials is targeting EUV and GAA
Chipmakers need to keep improving power, performance, area, cost and time to market (PPACt) as transistor and wiring structures become harder to pattern and manufacture. EUV and GAA tackle different parts of that problem: EUV is a patterning technology, while GAA is a transistor architecture. Their manufacturing needs overlap because both depend on precise control of materials and dimensions at very small scales.
Applied Materials described seven EUV and GAA innovations in an April 2022 announcement. They covered hardmask deposition, etch, eBeam metrology, epitaxy, atomic layer deposition (ALD), selective materials removal and integrated gate-stack solutions. In that announcement, Dr. Prabu Raja, then senior vice president and general manager of Applied Materials’ Semiconductor Products Group, said the innovations were designed to help customers continue 2D scaling with EUV.
The company’s subsequent announcements extend that strategy toward 2nm-and-beyond logic. In 2024, Applied reported a wiring integration using ruthenium with copper that reduced resistance by as much as 25%. In 2026, it announced additional deposition, etch and treatment systems for GAA structures and advanced logic. These are company-reported capabilities and results, not independent comparisons of complete chip-manufacturing processes.
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What EUV patterning changes—and why it still needs other tools
EUV lithography can print smaller features, but printing a pattern is only part of making it into a usable structure. The pattern must be transferred through resist and underlying transfer layers, including hardmasks. Variation can arise during that transfer, including stochastic defects and errors in where feature edges land. A small printed feature is not useful if the transferred pattern is inconsistent across the wafer.
Deposition and etch transfer the pattern
Applied presented Stensar Advanced Patterning Film as a hardmask deposition technology and Sym3 as a platform with etch and deposition capabilities. In the company’s 2022 description, these technologies were intended to improve pattern uniformity and reduce variability during pattern transfer. Deposition establishes films with the properties needed for later processing; etch removes selected material to reproduce the intended pattern in underlying layers.
Metrology helps find pattern problems
PROVision eBeam metrology was presented as a way to diagnose defects and assess patterns across the wafer. Measurement matters because process tuning depends on distinguishing a local defect from broader variation and identifying where a pattern transfer has gone wrong. Metrology can inform process control, but it does not itself correct a defect or guarantee yield.
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How GAA differs from FinFET
FinFET transistors use a channel formed in a vertical fin, with the gate controlling the channel from multiple sides. In a GAA design, the channel is arranged as horizontal nanosheets, and the gate surrounds each channel. That geometry gives the gate control around the channel rather than only along the exposed sides of a fin.
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GAA therefore changes the device structure as well as the manufacturing task. The nanosheets, the spaces between them, and the surrounding gate materials must be formed and controlled with high precision. Applied’s April 8, 2026 announcement says the nanosheets are spaced around 10 nanometers apart and that building the three-dimensional structures inside a GAA transistor takes more than 500 process steps. Both figures are Applied Materials’ descriptions; the step count refers to building the GAA structures, not the total number of steps in making a complete chip.
Epitaxy and selective removal shape the channels
Epitaxy grows crystalline material in a controlled way, while selective removal takes away chosen materials without removing adjacent ones to the same degree. Applied’s 2022 portfolio included both capabilities. The company described them as ways to tune channel width and uniformity, important because inconsistent nanosheet dimensions can produce inconsistent transistor behavior.
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ALD and gate-stack integration fill narrow spaces
The gate must conform to the nanosheet surfaces and fit into the narrow gaps around them. Applied described ALD and integrated materials solutions for building conformal oxide and metal gates in spaces around 10 nanometers wide. Its April 2026 announcement introduced Endura Trillium ALD and related deposition systems for tuning gate metals and threshold voltage in these structures. This is a materials-control problem as much as a geometry problem: the deposited layers and their properties affect how the transistor operates.
How the EUV and GAA approaches compare
| Manufacturing concern | EUV patterning support | GAA transistor fabrication |
|---|---|---|
| Primary role | Print and transfer very small patterns into material layers. | Build a transistor with horizontal nanosheet channels surrounded by a gate. |
| Applied technologies described | Stensar Advanced Patterning Film, Sym3 etch/deposition capabilities and PROVision eBeam metrology. | Epitaxy, selective materials removal, ALD and integrated gate-stack solutions; 2026 announcements also name Endura Trillium ALD, Sym3 Z Magnum conductor etch, Viva pure-radical treatment and Spectral molybdenum-contact deposition. |
| Key control problem | Reduce variation and edge-placement problems as a lithographic pattern is transferred through resist, transfer layers and hardmasks. | Control nanosheet dimensions and uniformity, then form conformal gate and contact materials in tight three-dimensional spaces. |
| Metrology need | eBeam measurement can help diagnose defects and pattern variation across the wafer. | The announcements describe demanding dimensional and materials control; the supplied product descriptions do not specify a separate GAA-specific metrology tool. |
| Process complexity | The announcements identify multiple pattern-transfer stages and tool types but do not state a total EUV process-step count. | Applied said in April 2026 that building the structures inside a GAA transistor takes more than 500 process steps. |
| PPACt and yield implications | Improved pattern uniformity and defect diagnosis may support process control; no quantified yield or PPACt improvement is stated for the EUV tools. | Channel and gate-material control supports transistor design goals; no quantified yield or overall PPACt improvement is stated for the GAA tools. |
| 2nm-and-beyond readiness | Applied positions the technologies as enabling continued scaling with EUV; the announcement does not establish adoption across all manufacturers. | Applied said in February 2026 that multiple leading foundry-logic manufacturers were using its Sym3 Z Magnum, Viva and Spectral systems. That statement does not by itself establish volume production at a particular node. |
Which Applied Materials tools are associated with 2nm-and-beyond logic?
Applied’s February 10, 2026 announcement names three systems for 2nm-and-beyond logic: Sym3 Z Magnum conductor etch, Viva pure-radical treatment and Spectral molybdenum-contact deposition. The company said multiple leading foundry-logic manufacturers were using these systems. The announcement supports a claim of use by those manufacturers, but does not identify them or specify whether each tool is deployed in a particular production line or node.
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Why wiring materials matter alongside transistors
Scaling challenges do not stop at the transistor. Wiring resistance affects how signals and power move through a chip, and interconnects also matter in three-dimensional stacking. In 2024, Applied reported that a ruthenium integration for copper wiring reduced resistance by as much as 25%. That is a company-reported maximum for the described integration; it should not be read as a guaranteed reduction for every wiring level, product or process.
What the announcements establish—and what they do not
Applied’s announcements describe equipment aimed at pattern transfer, GAA formation, gate-stack control and wiring integration. Together, they show why advanced manufacturing relies on coordinated deposition, etch, selective removal, treatment and measurement rather than on lithography or one standalone tool alone. For GAA, Applied’s stated figure of more than 500 process steps illustrates the integration burden within the transistor structures themselves.
- The announcements do not provide independent head-to-head performance data against other equipment suppliers.
- They do not quantify the resulting yield, chip speed, power consumption or total cost improvement for a finished product.
- Applied’s statements about use by multiple foundry-logic manufacturers do not disclose customer identities or establish the production status of each system at a named node.
Accordingly, the clearest supported conclusion is that Applied is broadening its process-tool portfolio around the manufacturing problems created by EUV pattern transfer and GAA’s three-dimensional structures. The evidence describes an equipment strategy and reported customer use, not a guarantee that any one tool determines a chip’s final PPACt or readiness for volume production.
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