At the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits, prioritize sessions that connect a compelling chip-level claim to implementation evidence: device or process choices, architecture, measured results, and trade-offs. The five-day, in-person event runs June 14–18 at the Hilton Hawaiian Village in Honolulu under the theme “Advancing the AI Frontier through VLSI Innovation.” Official symposium overview
Start with the evidence behind the AI theme
AI is the theme, not a reason to attend only sessions labeled AI. The call for papers spans devices and accelerators for machine learning and deep learning, processing and computing in memory, processors and SoCs, memory technologies, and advanced CMOS. 2026 call for papers
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When comparing AI-related talks, look for implementation detail: the process or devices used, memory hierarchy, data movement, accelerator architecture, measured efficiency, reliability, and whether results come from silicon. A broad claim about AI capability is less useful than a clear account of what was built, how it was evaluated, and what limits remain.
Follow scaling, power delivery, and packaging
Advanced CMOS and power delivery
Sessions on advanced CMOS, interconnect, and backside power-delivery networks address how chips can scale while meeting power and performance goals. Evaluate the evidence—such as density, performance, power, yield, variability, or design-enablement impact—rather than treating a process-node label as a result by itself. These areas are included in the 2026 call for papers.
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Chiplets and heterogeneous integration
The program includes 2.5D and 3D integration and chiplet-related work. For these sessions, listen for details on thermal behavior, bandwidth and latency, test strategy, and known-good-die economics. Integration can improve system capability, but its practical value depends on these engineering and manufacturing constraints.
Compare memory work by its system-level payoff
Memory technologies and computing or processing in memory are among the stated program areas. When evaluating a new cell or device, look beyond novelty to circuit-level benefits and the conditions under which they hold.
- For conventional memory, consider endurance, reliability, and how the technology fits the system.
- For compute-in-memory, look for analog accuracy, software mapping, and measured relevance to actual workloads.
- For either approach, distinguish demonstrated results from projected benefits.
Make room for circuits and applications beyond digital logic
The symposium’s scope also includes analog and mixed-signal circuits, data converters, frequency generation and clocking, signal integrity and I/O, power management, sensors, imagers, MEMS, displays, biomedical devices, and hardware security. The call for papers lists these fields. Choose these sessions when your work depends on interfaces, sensing, power, safety, or security—not just compute throughput.
Use the daily schedule to choose what to attend
The program format changes over the week. Plan around the distinction between learning and networking events early on and the technical sessions later. The official onsite guide gives this schedule:
Rank #3
| Day | Program | How to use it |
|---|---|---|
| Sunday, June 14 | Workshops | Choose a focused discussion or learning format before the main technical-session days. |
| Monday, June 15 | Short courses, demo session and reception, evening panel | Use courses for structured depth and the demos, reception, and panel for discussion and networking. |
| Tuesday, June 16 | Plenary and technical sessions | Reserve time for the technical tracks most relevant to your work. |
| Wednesday, June 17 | Plenary and technical sessions | Continue with priority sessions and account for any schedule conflicts. |
| Thursday, June 18 | Technical sessions and joint luncheon | The joint luncheon requires separate registration. |
When deciding between options, compare technical depth (symposium sessions versus short courses), format (workshops, demos, and panel), access timing (in-person Honolulu sessions versus later OnDemand), and total cost. Registration may combine a base option with an optional short-course/workshop bundle; the joint luncheon is separately registered. The registration page notes late rates after May 15, 2026, so check its current details before making plans. Registration information
Use last year’s highlights as context, not a forecast
The 2025 symposium in Kyoto had the theme “Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth.” One official technical highlight was Intel’s 18A RibbonFET and Power Via work. Intel’s highlighted paper stated that the platform provides “over 30% density scaling and a full node of performance improvement compared to Intel 3.” 2025 event context Intel technical highlight
That figure is Intel’s claim for the highlighted work, not an independently verified, industry-wide comparison. It is a useful example of the kind of quantified claim to examine carefully: identify the baseline, the metric, and who is reporting the result.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Check what registered attendees can access online
Registered attendees can retrieve PDF papers, presenter slides, proceedings, and OnDemand videos. Registration and login are required. OnDemand access opens June 22, 2026, after the in-person event. Workshop and short-course presentation files are available only through the online agenda and mobile app, according to the digital-access information.
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