SurgeonQ is a collaboration announced on 6 February 2025 by IQM Quantum Computers, Riverlane and Zurich Instruments. It combines Riverlane’s Deltaflow error-correction stack, an IQM 20-qubit superconducting processor and Zurich Instruments’ real-time control system to develop more flexible quantum error correction (QEC). Its goals include QEC cycle times on the order of a microsecond and a roadmap toward thousands of logical qubits. Those are project targets—not evidence that SurgeonQ has already delivered a fault-tolerant quantum computer.
What is the SurgeonQ quantum error-correction partnership?
SurgeonQ brings together three companies to work on the parts of a quantum-computing system that must coordinate for error correction: the processor, the control layer and the software that detects and corrects errors. The partnership’s announced technical focus is lattice surgery, a way of carrying out operations on logical qubits encoded across multiple physical qubits.
The name refers to a development collaboration, not a commercially available quantum computer or a claim that large-scale fault tolerance has already been achieved. In the 6 February 2025 announcement, the companies described a project intended to advance real-time QEC and set out a scaling objective.
What does each partner contribute?
| Partner | Contribution described in the 6 February 2025 announcement | Role in the system |
|---|---|---|
| Riverlane | Deltaflow QEC stack | Processes error information to detect and correct errors in real time. |
| IQM Quantum Computers | A 20-qubit superconducting processor and experimental implementation expertise | Provides the quantum hardware on which the QEC work is to be implemented. |
| Zurich Instruments | Integration of its Quantum Computing Control System | Connects processor data and QEC processing so they can communicate in real time. |
The system depends on these components working together: the processor produces measurements, the control layer manages communication with the hardware, and the QEC stack uses the resulting information to determine error-correction actions. The announcement presents real-time integration—not any single component in isolation—as central to the effort.
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What is lattice surgery, and why is SurgeonQ focused on it?
A physical qubit is a hardware-level quantum bit. A logical qubit is encoded across multiple physical qubits so that the system can detect and correct errors affecting the encoded information. Lattice surgery carries out logical operations by merging and reshaping clusters of qubits arranged in a two-dimensional lattice.
That makes lattice surgery a practical focus for the collaboration: it concerns not just storing encoded information, but performing operations on it while coordinating error correction. The partners say their system is intended to switch among multiple QEC routines in real time. They contrast that goal with systems that use one predefined QEC operation to minimize latency, a choice that can constrain flexibility.
What performance is SurgeonQ targeting?
The partners stated a target of QEC cycle times “in the order of a microsecond.” A QEC cycle is part of the repeated process of gathering information about errors and applying corrections. The target is meant to support complex QEC tasks and switching between routines without compromising computational speed.
This figure is an announced objective, not a reported measurement of a completed SurgeonQ system. The announcement does not establish that the target cycle time has been demonstrated on the combined platform, nor does it give a measured logical-error rate or a demonstrated count of logical qubits.
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No. The partners described a project and a roadmap toward commercial-grade fault tolerance, not a delivered system shown to meet that standard. In particular, the announcement’s 20-qubit figure describes IQM’s processor contribution; it is not a count of logical qubits, and it does not establish that thousands of logical qubits are available today.
The end-of-project objective is a roadmap for scaling QEC implementation to thousands of logical qubits and moving toward commercial-grade fault-tolerant quantum systems. A roadmap is a planned outcome. It should not be read as proof that the project has already built or deployed such a system.
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How does Deltaflow fit into the longer-term scaling picture?
Riverlane describes Deltaflow as a real-time QEC system intended to turn noisy physical qubits into reliable logical qubits. Its product material also identifies a roadmap toward one million real-time quantum operations. That is Riverlane’s broader product-roadmap claim; it is distinct from SurgeonQ’s announced project objective of developing a path toward thousands of logical qubits.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What would show whether a QEC platform is genuinely scaling?
For SurgeonQ or another platform, useful evidence goes beyond hardware size or a roadmap. Compare platforms across the same dimensions, and distinguish measured results from targets:
Quick Recap
- Hardware modality and qubit type: for SurgeonQ, the announced processor contribution is a 20-qubit superconducting system from IQM.
- Decoder latency and QEC cycle time: distinguish the announced microsecond-order target from a demonstrated cycle time under specified conditions.
- Flexibility: check whether the platform can switch among QEC codes or routines, rather than only execute one predefined operation.
- Integration: assess how processor measurements, control electronics and the decoder communicate and coordinate in real time.
- Demonstrated logical performance: look for measured logical-qubit counts and error performance, keeping them separate from roadmap goals.
- Availability: establish whether the system is a research platform, cloud-accessible service or commercial product.
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