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Tabula’s ABAX2P1 was a 22nm programmable logic device designed to process demanding network traffic, with Tabula reporting fabric operation up to 2GHz and capability to handle four 100G streams on one chip. Those were vendor-announced capabilities, not independently verified benchmark results. ABAX2 is now best understood as a notable historical architecture: the available announcements document customer development-system shipments in 2014, but do not establish whether the hardware or its support remains available today.
What was Tabula’s ABAX2P1?
ABAX2P1 was the first device in Tabula’s ABAX2 P-series of 3D programmable logic devices, or 3PLDs. Tabula combined programmable logic and other resources with its patented Spacetime architecture, which treated time as a third dimension in the design. Resources were arranged in repeated configuration “folds,” allowing the device to reuse them across successive time slices.
The distinction matters when interpreting ABAX2’s headline frequency. A quoted 2GHz fabric rate describes operation within the programmable fabric; it does not mean that every external interface ran at 2GHz or that a 100G network link itself had a 2GHz clock. The device was manufactured using Intel’s 22nm Tri-Gate process, according to Tabula’s 2012 announcement and contemporaneous EE Times coverage.
What did the published specifications say?
The figures below were reported by Tabula or reproduced from its specifications in contemporaneous coverage. They describe claimed device capabilities, not a common independent test.
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| Specification | Published figure | Source and qualification |
|---|---|---|
| Programmable-fabric operation | Up to 2GHz | Tabula, as reported by EE Times in 2013; the figure is an upper limit, not a statement that every design or workload reaches it. |
| On-chip memory | 23.3MB of 12- and 24-port memory | Tabula specification reproduced by EE Times in 2013. |
| On-chip-memory throughput | 13.8TB/s | Tabula specification reproduced by EE Times in 2013; this is the stated on-chip memory throughput, not an external network rate. |
| DDR3 controller rate | 2.133GT/s | Tabula specification reproduced by EE Times in 2013. |
| 100G stream processing | Four 100G streams on one ABAX2P1 | Tabula announcement reported by EDN and EE Times in 2013; the available account does not provide an independent benchmark methodology. |
| TSE2 search rate | 150 million searches per second per core; up to 600 million with four engines | Tabula and Algo-Logic announcement in 2013; the rate is a stated search-engine capability. |
What did “100G” mean for ABAX2?
Tabula’s 100G claims concerned packet-processing system designs, rather than a claim that the chip was a network transceiver. The company described designs for a 12×10G-to-100G bridge, a four-by-100G switch, and a ternary search engine for 100G packet traffic. It also announced that a single ABAX2P1 could process four 100G streams.
These examples addressed different networking tasks: bridging traffic from multiple 10G links, switching among 100G streams, and searching packet fields. The “four 100G streams” statement is a capacity claim in Tabula’s 2013 announcements; it should not be read as evidence that every customer design sustained that rate under every packet size, traffic pattern, or feature configuration. The available accounts do not give a reproducible independent test setup or results for such comparisons.
Rank #2
- ■High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX architecture (see Ta b l e 1)
- ■3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability–ISP circuitry compliant with IEEE Std. 1532
- ■Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
- ■Enhanced ISP features:–Enhanced ISP algorithm for faster programming–ISP_Done bit to ensure complete programming–Pull-up resistor on I/O pins during in–system programming
- ■High–density PLDs ranging from 600 to 10,000 usable gates
Packet search with TSE2
Tabula and Algo-Logic described the TSE2 ternary search engine as capable of 150 million searches per second per core, scaling to 600 million searches per second with four engines. This relates to packet classification and lookup, where ternary matching can represent entries with “don’t care” bits. The announced rate is specific to the TSE2 search engine; it is not a general-purpose ABAX2 application rate.
How did the Spacetime design and Stylus software fit together?
ABAX2’s repeated configuration folds were central to Tabula’s Spacetime approach. Instead of treating the programmable resources only as a spatial arrangement, the architecture also used time as a dimension. That approach was intended to make high-performance logic and resource reuse part of the device’s design model.
Rank #3
Designers used Tabula’s Stylus compiler with standard RTL inputs and design constraints. The software handled synthesis, placement, routing, and sequential-timing optimization for ABAX2P1. Tabula announced Stylus revision 2.6 support for ABAX2P1 in March 2013. This workflow was the vendor’s means of turning an RTL design into a placed-and-routed implementation; the published material does not establish how consistently independent design teams achieved the headline frequency or throughput.
What development systems did Tabula ship?
On September 10, 2014, Tabula announced first customer shipments of its 100G development systems. The announced package included:
Rank #4
- The logic for each channel sampling rate of 24M/s. General applications around 10M, enough to cope with a variety ofoccasions; 8-channel
- Sampling rate up to: 24 MHz , can be 24MHz. 16MHz, 12MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500KHz, 250KHz, 200KHz, 100KHz, 50KHz, 25KHz;
- The logic for each channel sampling rate of 24M/s. General applications around 10M, enough to cope with a variety ofoccasions;
- Input voltage range: -0.5V to 5.25V; Input Low Voltage: -0.5V to 0.8V; Input High Voltage: 2.0V to 5.25V
- Input Impedance: 1Mohm || 10pF (typical, approximate); Crystal: +/-20ppm, 24MHz
- An ABAX2P1 mounted on a development board.
- Stylus software.
- RTL reference designs and testbenches.
- Customer-portal documentation and training.
- Access to soft-IP libraries.
Tabula had earlier said engineering samples of ABAX2P1 would be available in the third quarter of 2013. These milestones indicate an engineering-sample plan followed by customer shipments of development systems; they do not by themselves establish broad retail availability.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can you still buy or get support for ABAX2?
Current availability is unresolved. The documented availability information is historical: Tabula’s engineering-sample plan dates to 2013, and its development-system shipment announcement dates to 2014. The available material does not confirm continued production, software support, or a successor as of 2026. ABAX2P1 and its development systems are specialized historical hardware, not products with an evidenced current retail listing.
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For someone seeking a board today, the practical next step is to verify directly with a seller or the relevant rights holder that a specific ABAX2P1 board is genuine, complete, and accompanied by usable Stylus tools and design files. A generic FPGA evaluation board is not an ABAX2 replacement: compatibility depends on the device architecture, toolchain, reference designs, and any required soft IP.
Were the 2GHz and 100G figures independent benchmarks?
No independent, reproducible benchmark methodology is established by the contemporaneous material summarized here. EE Times, EDN, PR Newswire, and the Algo-Logic announcement reported vendor specifications or announcements; those reports document what Tabula claimed and what it shipped, but do not turn the figures into third-party comparative results.
The figures are still useful for understanding the ambition of ABAX2: a programmable fabric advertised up to 2GHz, unusually high stated on-chip memory bandwidth, and packet-processing designs aimed at 100G systems. They should be cited with their source, date, and vendor-claim context rather than presented as independently measured superiority over other programmable devices.
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