A 130 nm process node is the name of a semiconductor manufacturing generation—not a claim that every transistor or other chip feature measures 130 nanometers. For example, Intel described its 130 nm process in 2000 as having a 70 nm transistor gate and a 1.5 nm gate oxide. The label is useful shorthand for a generation’s process and design capabilities, but the dimensions of individual features depend on the specific process.
What “130 nm” means
A nanometer is one-billionth of a meter. In semiconductor manufacturing, a process node is a generation label associated with manufacturing technology and the design capabilities available for that generation. Historically, node names tracked physical scaling metrics more closely than many modern leading-edge labels do—but the name was never a guarantee that every important feature had that exact dimension.
The 2003 International Technology Roadmap for Semiconductors (ITRS) discussion used DRAM interconnect half-pitch as a representative feature for node scaling. The Joint Research Centre describes earlier node names as coinciding with gate length and pitch, followed by half-pitch becoming the measure used. It also notes that below 28 nm, names no longer correspond to a specific feature size or a meaningful, measurable wafer transistor-density quantity. These historical conventions help explain node naming, but they do not turn a node label into a universal specification.
Does a 130 nm node mean the transistor is 130 nm wide?
No. The label does not tell you that every transistor is 130 nm wide, or that a particular transistor dimension is exactly 130 nm. Different measurements describe different parts of a device or wiring layer, and a process-generation name is not a complete dimensional specification.
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Intel’s 2000 announcement is a concrete example: its 130 nm logic process had a 70 nm transistor gate and a 1.5 nm gate oxide. Those are Intel-specific measurements, not universal dimensions for every manufacturer’s 130 nm process. The same announcement described copper interconnects, low-k dielectric, six layers of dual-damascene copper, and operation at 1.3 volts or less—details of Intel’s implementation rather than requirements implied by the node name. Intel’s November 7, 2000 announcement.
When did 130 nm manufacturing arrive?
The answer depends on which milestone you mean. Intel said it completed development of its 0.13-micron (130 nm) logic technology on November 7, 2000, and expected volume manufacturing to begin in 2001. Those dates describe Intel’s development announcement and forecast.
For DRAM production, the 2003 ITRS executive summary says the 2001 roadmap had anticipated a 130 nm ramp in 2001, while manufacturer data showed the actual qualified production ramp in 2002. A technology-development milestone, a roadmap target, and an industry production ramp are different events; they should not be treated as one universal launch date. The 2003 ITRS executive summary.
Why can two 130 nm processes differ?
A node name does not specify an identical menu of devices, materials, electrical characteristics, or design rules across foundries. TSMC’s 2003 discussion said that 130 nm and 90 nm device characteristics were no longer a straightforward extension of earlier generations, and highlighted the trade-offs involved in mixed-signal design. A designer evaluating a process therefore needs the foundry’s actual process documentation, not just its node label. TSMC’s discussion of its 130 nm technology.
Do these 3 things before closing this tab:
1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteFor a real design, compare process offerings on the characteristics that affect the application:
- Device variants and electrical behavior: Check which transistor options are available and whether their characteristics fit the circuit.
- Voltage, power, and performance: Confirm the requirements against the specific process rather than assuming a node number guarantees a particular operating voltage or speed.
- Analog and mixed-signal suitability: Assess the relevant device trade-offs and process options for the design.
- Integration and interconnect: Review supported density, interconnect choices, and design rules.
- Qualification and cost: Confirm manufacturing qualification and total design and production economics.
Why are 130 nm and other mature nodes still used?
Smaller geometry is not automatically better for every product. Texas Instruments said in 2024 that analog and embedded semiconductors in the 45 nm to 130 nm range remain ubiquitous. The company’s executives described applications across automobiles, industrial equipment, computers, and phone circuit boards, and argued that many such products do not need the smallest geometries. TI’s Amichai Ron said shrinking certain analog and RF transistor geometries could produce “a higher cost device with no performance benefits for our customers.” These are TI’s statements about its products and applications, not a claim that every design should use a mature node. TI’s March 20, 2024 article on mature-node chips.
The practical lesson is to choose a process for the requirements of the chip, not to select the smallest number on a technology list by default. A mature process may suit a design whose analog, embedded, voltage, cost, or manufacturing needs are better served by that specific offering.
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