A conventional CCD outputs a time-varying analog voltage, not a finished digital pixel. Each pixel period includes a reset reference level and a charge-dependent signal level; the useful pixel value is their difference, measured after the waveform has settled. The output polarity and exact timing depend on the sensor and readout circuit.
What a CCD output signal represents
In a typical floating-diffusion CCD, photons generate electrons that are collected as charge packets. Clock pulses move those packets through the image and horizontal registers to an output gate and then onto a floating-diffusion sense node. The node converts charge into voltage, and an output transistor buffers that voltage for external circuitry. The signal path is therefore:
Photons → photoelectrons → charge packets → horizontal register → output gate → floating diffusion → output transistor → analog waveform → analog front end (AFE) and ADC.
The sense-node voltage change is approximately ΔVFD = Q/CFD, where Q is transferred charge and CFD is the effective node capacitance. The output stage has its own gain, often below unity for a source-follower arrangement, so the voltage seen at the output pin also depends on that gain, bias, loading, and operating speed. Hamamatsu describes the floating-diffusion and output-amplifier chain in its CCD overview.
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Consequently, image brightness is not represented by the output’s absolute DC voltage. It is represented by the change between the reset/reference level and the signal level. Depending on output architecture and downstream inversion, that difference may be defined as reference minus signal or signal minus reference.
How one pixel looks on an oscilloscope
A simplified pixel waveform has a reset transient, a settled reference interval, a charge-transfer event, and a settled signal interval. The diagram is conceptual; the exact waveform shape and timing vary by sensor and circuit.
reset feed-through charge transfer
/ ↓
reset level _/ ________ reference level ________________ signal level
|<----------- one pixel period ---------------->|
The pixel period is approximately Tpixel = 1/fpixel. At a 2.5 MHz pixel rate, for example, the nominal period is 400 ns; this is arithmetic, not a universal CCD timing specification. That interval must accommodate reset, settling, charge transfer, further settling, sampling, and the ADC aperture. A Hamamatsu S15351-2048 datasheet shows an example waveform at 2.5 MHz with a 2.2 kΩ load, conditions specific to that example rather than a general recommendation: S15351-2048 datasheet.
Real traces need not resemble clean square steps. They can have rounded edges from bandwidth limits, settling tails, clock coupling, output-amplifier noise, multiple or alternating output channels, and either signal polarity. Other Hamamatsu examples use different sensor conditions and loads, including 100 kΩ; follow the exact device datasheet rather than copying a load value from another model. See the S14651/S14661 series datasheet.
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Reset level, signal level, and feed-through
Reset or reference level
Before a charge packet is measured, the reset transistor returns the sensing node to a reference voltage. The resulting plateau is called the reset level or reference level. Reset is not perfectly noiseless: thermal reset uncertainty, commonly described as kT/C noise, can make the post-reset voltage vary from pixel to pixel. See Hamamatsu’s explanation of CCD noise and reset noise.
Signal or data level
When a charge packet reaches the sense node, its voltage changes, producing the signal level. The difference between the settled reference and signal plateaus is proportional to packet charge. In many designs, adding electrons lowers the node voltage and produces a downward step, but polarity is device-specific and can also be reversed by an inverting amplifier or AFE subtraction setting. Check the sensor datasheet’s “OS output waveform” or equivalent timing diagram.
A useful model is ΔVCCD = Gout Q/CFD, with Gout the output-stage voltage gain. Datasheets may instead specify conversion sensitivity in microvolts per electron or another unit. As a purely illustrative calculation, let CFD = 10 fF and let the packet contain 1,000 electrons. Then Q = 1,000q ≈ 1.60 × 10−16 C, giving Q/CFD ≈ 16 mV at the sense node before output-stage gain. These hypothetical values are not a specification or expected output for any particular CCD.
Reset feed-through
Reset feed-through is a transient coupled into the output when the reset gate switches. It may appear as a spike or sharp disturbance, but it is not the pixel’s photocharge signal. Clock transitions can add further coupling. The reference sample should be taken after the transient has settled, not on its peak. Poor timing, inadequate settling, or front-end saturation can leave artifacts even when CDS is used. Hamamatsu discusses CCD output waveforms and readout timing in its CCD technical note.
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How correlated double sampling extracts the pixel
Correlated double sampling (CDS) measures two levels from the same pixel period and subtracts them. The reference sample is taken during the settled reset interval; the data sample follows charge transfer and signal settling. Their difference ideally represents the charge-dependent signal. TI describes these as reference and video samples in its CCD AFE overview.
- Reset the sensing node.
- Allow reset feed-through to settle, then sample the reference level.
- Transfer the charge packet to the sensing node.
- Allow the signal level to settle, then sample the data level.
- Subtract the samples using the polarity appropriate to the sensor and AFE.
- Apply gain and offset handling, then convert the conditioned result with an ADC.
Implementations include dual sample-and-hold circuits followed by a differential amplifier, clamp-and-hold circuits, switched-capacitor circuits, integrated CCD AFEs, and digital subtraction after ADC conversion. TI AFE timing often labels the reference and data sample controls SHP and SHD; the correct sample positions are device-specific, not fixed percentages of a pixel period. See the VSP2582 datasheet and VSP5611 datasheet.
CDS reduces reset kT/C noise, common offsets, and some low-frequency or correlated output noise because those components are shared by the paired samples. It does not eliminate noise. Photon and dark-current shot noise, uncorrelated amplifier noise, high-frequency clock coupling, transfer inefficiency, quantization noise, pattern noise, residual flicker noise, and noise from the CDS circuit itself can remain. The amount of reduction depends on timing, bandwidth, topology, and settling. TI and Analog Devices discuss these limits in their VSP2582 documentation and imaging AFE article.
Why the raw output needs conditioning before an ADC
The raw CCD waveform can ride on a substantial DC offset. Sending it directly to an ADC may spend much of the converter’s range on that offset and transient rather than on the pixel difference. A representative readout chain is:
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CCD output → protection and coupling → clamp or DC restoration → CDS → programmable-gain amplifier (PGA) → black-level correction → ADC → digital image corrections.
- Clamp or DC restoration: establishes a usable common-mode level after AC coupling.
- CDS: extracts the reference-to-data difference.
- PGA: scales the signal to suit ADC range and desired resolution.
- Black-level correction: removes baseline offsets, often using optical-black pixels.
- ADC: converts the conditioned analog pixel value into a digital code.
- Timing generator: coordinates reset, transfer, sample windows, and conversion.
AC coupling and clamping require care: capacitor choice, bias current, clamp-reference capacitance, and clamp timing can cause baseline errors. Large transients may saturate input circuitry and create a recovery interval longer than the visible spike. TI explains clamp behavior and transient recovery in its CCD AFE description. Integrated AFEs can combine clamp, CDS, PGA, ADC, optical-black processing, timing, or references; one example is documented in the VSP2582 datasheet.
How to read a CCD datasheet waveform
- Find the output pin and architecture. Confirm whether the described output is a floating-diffusion/source-follower output or another arrangement; the explanation and polarity may differ.
- Check the stated conditions. Note pixel frequency, output load, bias voltages, clock levels, and any external circuit shown. Waveform examples are conditional measurements, not universal templates.
- Locate the reset transient and plateau. Distinguish feed-through from the settled reference interval.
- Locate the charge-transfer event and signal plateau. The pixel information is the difference between the two settled levels.
- Read timing labels and polarity. Match the diagram to the sensor’s output and the AFE’s sample controls; do not assume every CCD has the same polarity or sample locations.
The reset-drain bias and output-drain operating point also matter. Hamamatsu notes that inadequate output-drain bias can reduce source-follower gain, move the MOSFET out of saturation, increase read noise, reduce conversion sensitivity, or worsen linearity. Consult the exact sensor’s recommended bias and load circuit in its technical note.
Measuring the output safely and usefully
- Read the exact sensor datasheet. Identify the OS output, required output load, output-drain and reset-drain biases, clock levels, maximum pixel rate, and recommended circuit.
- Match the specified load and bias network. Do not connect an arbitrary 50 Ω scope termination unless the datasheet permits it; loading can change gain, bandwidth, settling, and noise.
- Use a short ground connection or suitable differential probe. Long probe ground leads can turn clock edges into apparent output noise.
- Start at a low pixel rate and show several pixels. Slower operation makes the plateaus easier to separate; multiple periods reveal repeating or alternating channel effects.
- Identify feed-through, then measure settled plateaus. Use consistent timing across pixels and avoid transitions for both measurements.
- Check polarity by changing illumination or integration time. Observe whether the signal step moves up or down rather than inferring sign from a generic diagram.
- Compare dark and illuminated traces. A dark trace helps reveal reset noise, clock coupling, baseline drift, and amplifier noise; increase illumination carefully to observe growth before saturation.
- Adjust CDS timing and gain only after the waveform is understood. Use the sensor timing diagram and AFE constraints to set the sample windows.
A functioning readout should show a repeatable pixel cadence, stable reset and signal regions, and a charge-dependent difference that responds to illumination or integration time. The absolute pin voltage can be much larger than the image signal because of the DC offset. Hamamatsu’s waveform example and Analog Devices’ discussion of offset and ADC range provide context: Hamamatsu example and Analog Devices article.
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Troubleshooting common waveform problems
| Observed problem | Likely causes | Checks |
|---|---|---|
| No visible pixel structure | Missing horizontal clocks, incorrect output bias or load, sensor not powered, or excessive bandwidth limitation | Confirm clock sequence, OS bias, output-drain supply, and the specified load. |
| Large spike but no stable signal plateau | Viewing or sampling feed-through, charge not reaching the output node, or incorrect summing-gate timing | Compare summing-gate timing with the sensor timing diagram. |
| Signal polarity is reversed | Device polarity, an inverting stage, or reversed CDS subtraction | Verify the sensor waveform and AFE polarity configuration. |
| Baseline slowly drifts | Clamp-loop error, AC-coupling time constant, temperature, dark current, or unstable bias | Compare optical-black pixels and monitor temperature and bias. |
| ADC clips although the image is dim | Large DC offset, insufficient clamp range, excessive PGA gain, or transient saturation | Inspect the pre-CDS waveform and AFE input range. |
| Repeating spikes at clock edges | Clock coupling, grounding or bypassing problems, or capacitive pickup | Observe clocks and output together and shorten probe connections. |
| Excessive read noise | Incorrect CDS timing, inadequate settling, noisy output bias, poor grounding, or excessive bandwidth | Move sample windows away from transitions and assess bandwidth. |
| Different outputs disagree | Gain or offset mismatch, timing skew, separate amplifier noise, or wiring error | Measure each output independently and calibrate digitally. |
| Signal changes when scope settings change | Probe capacitance or termination loading the source follower | Compare a compatible high-impedance probe with the specified load. |
Choosing a readout approach
Analog or digital CDS
Analog CDS subtracts before conversion, reducing the offset and range that the ADC must accommodate, but it depends on accurate analog timing, settling, and low-error clamp and sample circuits. Digital CDS digitizes enough of the raw waveform to subtract samples later, allowing flexible timing, averaging, and calibration; it also requires an ADC and input chain with sufficient range, speed, and noise performance. Digital CDS is used in scientific CCD readout, including astronomical systems; see this CCD readout paper. Neither method is universally preferable.
Gain, speed, and headroom
More PGA gain maps a small CCD difference across more ADC codes but reduces headroom and can cause clipping; less gain preserves bright-signal range but may leave ADC resolution underused. Gain does not automatically improve signal-to-noise ratio because it can scale noise along with signal. Faster pixel rates shorten settling and sampling windows, while slower readout generally gives more time for the output and external network to settle at the cost of throughput. Hamamatsu discusses the gain and noise relationship in its camera simulator.
Multiple outputs and channel matching
Large or fast CCDs may have multiple output amplifiers. Treat each as its own analog channel: offsets, gains, noise, timing skew, and fixed-pattern behavior can differ. The reconstructed image stream may therefore need channel-specific measurement and calibration.
Quick Recap
Quick readout checklist
- Can you identify the settled reset/reference and signal/data plateaus?
- Have you excluded reset feed-through and other transitions from the sample windows?
- Have you confirmed output polarity from the exact device waveform?
- Is the sensor loaded and biased according to its datasheet?
- Are the AFE input, clamp, and gain ranges compatible with the raw offset and transients?
- Are CDS sample positions aligned to the sensor’s transfer and settling times?
- Is the ADC receiving the conditioned pixel difference rather than an unclamped raw waveform?
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