TSMC has demonstrated research-stage liquid-cooling structures designed to remove heat close to high-performance silicon, including direct water cooling through channels in a silicon layer. Its 2021 work reported cooling test vehicles operating at kilowatt-class power, and a 2024 IEEE publication described a near-full-reticle die cooled at 2 kW. These are package and thermal demonstrations—not an announced CPU, GPU, or other retail chip with built-in water channels.
What TSMC means by on-chip water cooling
The phrase can suggest water flowing through a processor die itself. TSMC’s described approach is more accurately understood as direct liquid cooling at the silicon or package level: channels are etched into a silicon layer positioned close to the heat source, allowing coolant to remove heat without relying on the conventional path through a package lid and thermal interface material (TIM).
TSMC’s 2021 research describes a fusion-bonded silicon lid with trenches or grid-like structures and direct backside water cooling. The tested channel geometries included square pillars, trenches, and a flat plane. The aim is to shorten the thermal path between hot silicon and coolant; the work does not establish that water circulates through transistor structures.
What the demonstrations measured
The reported results are not all measurements of the same setup. They span a single-SoC test, a CoWoS package study, later large-die work, and a separate immersion-cooling project. The conditions and scope matter when comparing their numbers.
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|---|---|---|
| TSMC direct water-cooling research, 2021 | More than 2,600 W on a single SoC, equivalent to 4.8 W/mm²; more than 7 W/mm² demonstrated with direct water cooling on the logic-chip backside. | Thermal test-vehicle results reported by TSMC, not a retail-chip rating. |
| TSMC CoWoS liquid-cooling study, 2021 | Study covered thermal design power up to 2 kW. At a coolant flow rate of 40 ml/s, direct liquid cooling measured about 0.055 °C/W junction-to-ambient thermal resistance, compared with about 0.064 °C/W for a lidded cooler with TIM. | Package-study figures under the reported study conditions; lower thermal resistance means less temperature rise per watt across the measured junction-to-ambient path. |
| TSMC test data as summarized by a secondary report, 2021 | Up to 2.6 kW of heat dissipated at 5.8 L/min, with a 63 °C temperature delta. | A secondary account of presentation/test-vehicle data, not a product specification. The temperature delta is the reported difference for that test, not a general operating temperature. |
| IEEE ECTC publication, 2024 | A near-full-reticle die was cooled at 2 kW and 3.2 W/mm² using 40 °C water. | A later large-die demonstration with its inlet-water temperature specified; it does not imply that all other results used the same coolant conditions. |
| TSMC immersion-cooling project, 2022 | TSMC reported more than 10% higher computing performance in the described system and targeted annual savings of 400 million kWh from 2030. | System-level project claims and a future savings target, not measurements of an on-chip channel design or a guaranteed outcome for other deployments. |
TSMC’s 2021 research page described its CoWoS work as an “industry first advanced liquid cooling technology” for a package with TDP up to 2 kW. That wording refers to the study and its stated design scope; it should not be read as evidence of a commercially available 2 kW processor.
How the cooling approaches differ
| Approach | Where the coolant or interface sits | What the cited work establishes | Main practical consideration |
|---|---|---|---|
| Direct silicon water cooling | Water flows through channels in a silicon structure close to the logic-chip backside. | TSMC reported more than 7 W/mm² in its 2021 direct-cooling work and measured lower junction-to-ambient resistance than the compared lidded TIM cooler in its CoWoS study. | Bringing coolant close to silicon can reduce interface resistance, but requires reliable channel fabrication, sealing, coolant delivery, and package integration. |
| TIM-based cooling | A thermal interface material separates the die and a cooler or lid. | The 2021 CoWoS study reported about 0.064 °C/W for a lidded cooler with TIM, compared with about 0.055 °C/W for direct liquid cooling at 40 ml/s. | The interface helps keep liquid separate from active silicon and can simplify separation of components, but adds thermal resistance. |
| Immersion cooling | The server or system is immersed in coolant rather than having water channels built into a chip package. | TSMC’s 2022 project reported system-level performance and energy claims. | It addresses heat management at the server or facility level; it is not the same architecture as a silicon microchannel cooler. |
TSMC has also studied silicon-oxide and liquid-metal thermal-interface designs alongside direct water cooling. Those approaches vary the interface between the chip and cooling structure; the cited results do not establish that they share the same thermal performance or readiness as the specific direct-water test vehicles.
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- Stable 12TH/s High-Performance Computing Power Built with upgraded high-grade chip architecture, this computing system delivers consistent 12TH/s output with stable performance. It supports reliable 24/7 continuous operation, effectively preventing performance drop caused by high temperature, frequency reduction and unexpected downtime. Ideal for daily computing work at home, studio and small office
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Why cooling is becoming a package-design issue
AI and high-performance computing devices can concentrate substantial heat in a small area. As chip packages combine larger dies and more closely integrated components, removing heat through a conventional lid and interface can become a limiting part of the design, not just a matter of attaching a larger external cooler.
The packaging context is evolving: TSMC said CoWoS entered 3.5-reticle-size volume production in 2024, and said 3 nm SoIC chip stacking entered volume production in 2025. Larger package footprints and stacked silicon increase the importance of thermal engineering because heat must be extracted from densely integrated components while maintaining workable temperatures across the package.
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Direct liquid cooling could help by bringing coolant nearer the heat source. That may support higher power density or denser 2.5D and 3D integration, but the cited demonstrations do not show that it has already solved the manufacturing, reliability, or service challenges of production packages.
What would have to work before it reaches products
A thermal test vehicle can show that a cooling structure removes heat under test conditions. A commercial package also has to meet constraints that a headline wattage alone cannot answer:
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- Two direction copper cooling plate directly connects essential parts The thick copper base with multiple water channels ensures rapid heat removal from processing chips Its layout covers both the main chip and nearby power components
- Reinforced construction maintains stable action in tough environments Built for prolonged data center use, its refined internal water channels improve heat transfer capability
- For high efficiency computing cards, this liquid cooling radiator precisely fits select models SXM2 GPUs with unique architecture ( V100, P100, A100 32G), it includes accurate mounting holes and PCB alignment for optimal with processing chips and memory
- Enables sustained top levels function for complex calculations and machine learning processes Replacing standard air cooling provides greater thermal capacity, maintaining consistent processing speeds during neuronal net development, research simulations
- Coolant delivery and sealing: Channels and connections need to maintain flow without leaks over the product’s operating life.
- Manufacturing yield: Silicon channel fabrication and bonding must work consistently alongside the package’s other manufacturing steps.
- Electrical and long-term reliability: The cooling structure must not compromise nearby circuitry or package reliability.
- Serviceability: A package connected to coolant plumbing may be more involved to install, replace, or repair than a conventional cooled component.
- Data-center infrastructure: Direct-to-chip cooling needs compatible coolant distribution and facility planning; the package is only one part of the cooling system.
- Total operating cost: Cooling capacity must be weighed against pumps, plumbing, maintenance, and facility operation—not just the chip’s measured thermal resistance.
Is TSMC’s water-cooled chip available?
No generally available TSMC CPU, GPU, or other retail processor with integrated water channels is identified in the cited material. TSMC’s work is described as research, package studies, thermal test vehicles, and pilot infrastructure; it does not announce a customer product timetable. Commercialization remains unresolved, and generic PC liquid coolers are not the same technology: they cool a component externally rather than routing water through a silicon cooling structure close to the die.
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