TSMC 7nm is a family of chip-manufacturing processes, not a particular processor or a promise that every transistor measures exactly seven nanometers. The original FinFET process, N7, entered volume production in 2018. Later variants include N7+, which introduced selected EUV lithography layers, and N6, a related process designed to offer greater logic density and a practical migration path from N7. Their benefits depend on the specific process and chip design; a node name alone does not predict a finished product’s speed or battery life.
What does TSMC 7nm mean?
“TSMC 7nm” refers to a manufacturing technology node used to make logic chips at Taiwan Semiconductor Manufacturing Company (TSMC). It is a process family, with N7 as the original member and enhancements such as N7+ and N6. It does not identify a specific CPU, GPU, or phone chip.
The “7nm” label is a node name, not a guarantee that a transistor’s gate or every other feature is exactly seven nanometers wide. Nor is it a universal industry specification: node names from different manufacturers do not necessarily describe identical geometries or capabilities.
TSMC’s N7 uses FinFET transistors. In a FinFET, the transistor channel is formed in a raised fin, giving the gate more control over the channel than a conventional planar structure. That design helps engineers balance power and performance as transistors are scaled. TSMC’s explanation of transistor structure describes this approach.
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A process node sets some of the manufacturing options available to chip designers, but the final chip also depends on its architecture, layout, voltage, clock targets, cache, packaging, memory, cooling, software, and manufacturing yield. Node-level claims are therefore not a substitute for product measurements.
How the TSMC 7nm family developed
N7: the original 7nm process
TSMC’s original N7 is a 3D FinFET process. The company said it entered volume production in the second quarter of 2018 and offered separate process tracks optimized for mobile and high-performance computing (HPC). TSMC described N7 as one of its fastest technologies to reach volume production. TSMC’s N7 production announcement gives the production milestone and application context.
The original N7 implementation used conventional deep-ultraviolet (DUV) lithography rather than EUV. It should not be confused with N7+, which added EUV to selected layers.
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N7+: selected EUV layers
N7+ is an enhancement to the 7nm platform that uses EUV lithography on several layers. TSMC said it entered volume production in the second quarter of 2019 and was the foundry industry’s first commercially available EUV process. The company reported 15–20% greater density than N7, along with improved power characteristics. Those claims describe the process comparison, not a guaranteed improvement in every N7+ chip. TSMC’s N7+ announcement provides its stated comparison.
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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallEUV, or extreme ultraviolet lithography, is a patterning technique used to print selected features on a wafer. For some critical layers, it can reduce the multiple-patterning steps required with DUV and simplify parts of the manufacturing flow. N7+ is not simply N7 with every layer switched to EUV, and EUV by itself does not guarantee a faster or more power-efficient finished chip.
N6: a related 6nm migration option
N6 is branded as a 6nm process but is closely related to N7. It adds EUV layers and offers approximately 18% higher logic density than N7, according to TSMC. It was designed with compatible design rules and IP to make migration from N7 easier, and entered volume production in 2020. TSMC also described process simplicity, cycle time, and productivity benefits. TSMC’s N6 announcement covers the density comparison; its HPC technology page describes compatibility.
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Compatibility is not the same as an automatic or cost-free port. A chip moving from N7 to N6 may still require physical-design work, timing closure, verification, mask changes, IP qualification, yield learning, and product validation.
N7, N7+, and N6 at a glance
| Process | Production milestone | Lithography and relationship | Published density comparison |
|---|---|---|---|
| N7 | Volume production began in Q2 2018 (TSMC). | Original 7nm FinFET implementation; DUV rather than EUV. | Baseline for the N7+ and N6 comparisons below. |
| N7+ | Volume production began in Q2 2019 (TSMC). | FinFET process using several EUV layers; related to, but not identical to, N7. | TSMC reported 15–20% greater density than N7. |
| N6 | Volume production began in 2020 (TSMC). | Related 6nm process with additional EUV layers and design-rule compatibility intended to ease migration from N7. | TSMC reported approximately 18% higher logic density than N7. |
The distinctions matter because “7nm” does not tell you which process variant a chip uses. N7+, for example, should not be described as automatically 20% faster than N7: TSMC’s cited announcement emphasizes density and improved power characteristics, not a blanket speed gain.
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What performance gains did TSMC claim?
These figures are TSMC’s published process-level comparisons, not independent product benchmarks. “Up to” figures describe the company’s stated potential under its comparison conditions; they are not guaranteed results for every design.
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| Comparison | TSMC-published claim |
|---|---|
| N7 versus N16 | Up to 30% higher speed. |
| N7 versus N16 | Up to 55% lower power. |
| N7 versus N16 | Up to 3× the logic density. |
| N7+ versus N7 | 15–20% greater density, with improved power characteristics. |
| N6 versus N7 | Approximately 18% higher logic density. |
TSMC’s published figures have varied by announcement and comparison. In its 2018 announcement, the company compared N7 with 16FF+ and cited approximately 35% higher speed at the same power, or approximately 65% lower power at the same speed. Its current platform page instead states up to 30% higher speed, 55% lower power, and three times the logic density versus N16. These comparisons may use different process versions, targets, or methodologies; they should not be combined as if they were one universal specification. See the 2018 announcement and TSMC’s current advanced smartphone technology page.
Logic density is not the same as total chip performance or the number of transistors that every finished chip will contain. The result depends on what logic is being counted, how the design is laid out, and the performance, power, and area targets chosen by its designers.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Where TSMC’s 7nm-family processes are used
TSMC identifies applications across mobile computing, 5G, HPC, AI, server CPUs and GPUs, networking, FPGAs, gaming, automotive electronics, and digital consumer electronics. The process family was developed for mobile and HPC needs and later used across a wider range of markets. TSMC outlines these uses on its 7nm technology page and in its N7 announcement.
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Those broad categories do not establish which specific N7-family variant a particular product uses. A “7nm” label in product coverage may not tell you whether a chip was made on N7, N7+, or another related process, or which design libraries and packaging it uses. Specific chip attributions need confirmation from the chip designer, manufacturer, or a reliable technical analysis.
Is TSMC 7nm still relevant in 2026?
Yes. As of 2026, the N7 family is mature and widely deployed, but it is no longer TSMC’s newest leading-edge technology. TSMC’s 2025 annual-report material says N2 volume production began in 2025, after intervening generations including 5nm and 3nm. TSMC’s 2025 annual-report technology material documents that milestone.
A newer node may offer advantages in density or efficiency, but moving a design also brings development, qualification, and manufacturing considerations. A mature process can remain a reasonable choice when its performance, cost, qualified IP, availability, or product lifecycle fits the product better. That is particularly relevant to long-lived markets such as automotive and industrial electronics, where process choice is about the whole product and supply plan—not just which node is newest.
What should buyers make of a 7nm label?
For a device buyer, the node is background information, not a verdict on whether a product is fast, efficient, or worth buying. A well-designed chip on an older process can outperform a poorly optimized chip on a newer one, and a process-level power claim does not directly predict a phone’s battery life or a computer’s energy use.
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Compare the complete product using evidence relevant to your workload:
- Independent benchmark results, including sustained performance rather than short bursts.
- Measured power use, battery life, and thermal behavior in the actual device.
- CPU and GPU architecture, memory bandwidth, and software support.
- Price, availability, and the features the chip enables.
Questions about packaging and cooling matter too: performance is determined by the complete chip and system, not the process label alone.
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