Synopsys VCS 5.0, released in the week of February 15, 1999, was reported to deliver two-to-five-fold faster simulation runtimes, depending chiefly on how a Verilog design was written. The release reduced simulation events through technology Synopsys acquired from Radiant Design Tools, while retaining VCS’s overall event-driven execution model. It also added direct-kernel links for selected debugging tools.
How much faster was VCS 5.0?
Synopsys claimed a two-to-five-fold improvement in simulation runtime. That was a 1999 vendor claim, not a universal benchmark: the gain depended mainly on coding style, with most of the benefit appearing at the register-transfer level (RTL). Synopsys said there could be some improvement at every abstraction level.
The performance work drew on technology developed by Radiant Design Tools, which Synopsys acquired in January 1998. It took advantage of redundancy and uniformity in Verilog descriptions to reduce the number of simulation events. As Steve Smith, then director of marketing for Synopsys’ simulation technology group, put it: “It reduces the amount of effort a Verilog simulator will have to make by reducing the number of events.”
Was VCS 5.0 cycle-based or event-driven?
It was event-driven overall. VCS could run two-state, cycle-based simulation for suitable portions of Verilog, but it compiled all code into a single executable and did not replace its overall event-driven model with cycle-based simulation. The distinction matters: cycle-based execution was an option for appropriate design portions, not a description of the entire simulator.
Quick wins for a faster PC:
Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →#1 Best Overall
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
What did direct-kernel integration do?
VCS 5.0 optimized the standard Verilog programming-language interface (PLI), a way for external tools to interact with a simulator. It also offered a proprietary direct-kernel interface for selected tools. Those integrations could link a tool directly to the VCS simulation kernel, bypassing PLI overhead.
Named integrations
- Direct-kernel links were available for Summit Design’s VirSim graphical-analysis product and Novas Software’s Debussy debugging product.
- Synopsys said its Vera test-bench generation system and Eagle hardware/software coverification offering would also be linked.
Which standards and libraries did VCS support?
Synopsys said VCS 5.0 supported IEEE 1364 and Open Verilog International language and PLI standards. It also claimed support for more than 150 ASIC libraries and carried the SI2 library-qualification seal.
What platforms and price did the 1999 report give?
VCS 5.0 was available for Unix and Windows NT workstations. Node-locked licenses started at $30,000 in 1999. That figure is a historical starting price, not current pricing or a guide to present-day licensing.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the report does not establish today
EDN’s February 15, 1999 report documents the VCS 5.0 release and its claims at that time. It does not establish the current VCS release, present-day availability, pricing, or licensing terms.
Free tools Windows power users keep installed
One-click scans. No signup required.
Quick Recap
Rank #4
- [Powerful FPGA Core] Tang Nano 9K is built on the GOWIN GW1NR-9, featuring 8640 LUT4s, 6480 flip-flops, 468K B-SRAM, and 64M PSRAM. It supports the PicoRV RISC-V soft core, making it ideal for Verilog HDL learning, digital logic design, and complex circuit verification.
- [Rich Display Interfaces] Tang Nano 9K integrates HDMI, RGB LCD, and SPI LCD interfaces to support a variety of display output solutions, making it ideal for video processing, image output, and display-related prototyping.
- [Programming and Debugging] Tang Nano 9K is equipped with BL702 USB-JTAG and USB-UART, eliminating the need for an additional debugger; 6 programmable LEDs, 2 user buttons, 32Mbit SPI flash memory, and a TF card slot for expanded storage.
- [Flexible I/O] Configurable I/O interfaces with a drive current range of 4mA–24mA; equipped with 2 PLLs and 20 multipliers to support high-speed operations; all I/O pins are exposed, facilitating connection to various peripherals and project verification.
- [Application Scenarios] Whether you are an FPGA beginner, a RISC-V developer, or a seasoned hardware engineer, you will benefit from this board. It supports design using the Verilog HDL hardware description language, can run C/C++ code as an MCU, and supports co-design of hardware and software. It is suitable for prototyping, logic verification, embedded system design, and industrial control projects.
Rank #3
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
