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In 2005, Soitec reported using its Smart Cut wafer-splitting process to transfer a thin, single-crystal gallium nitride (GaN) layer onto an insulating layer over a GaN carrier wafer. The demonstration showed how the active GaN film could be separated from the support beneath it; it did not disclose the wafer diameter or establish a commercial product.
How Smart Cut transfers a GaN layer
Smart Cut combines light-ion implantation with wafer bonding. The process creates a weakened plane inside a GaN donor wafer, bonds that donor to a handle wafer, then splits the donor at the weakened plane. The thin film left on the handle retains the donor material’s single-crystal orientation.
- Implant the donor: Light ions are implanted into the GaN donor to define a buried, weakened plane.
- Bond the wafers: The donor is attached to the handle wafer through molecular-adhesion bonding.
- Split and transfer: The donor separates along the weakened plane, leaving a thin GaN layer on the handle.
Soitec developed the 2005 work with Picogiga International, its compound-semiconductor subsidiary, in a technology-development program with CEA-Leti. The resulting stack was GaN over an insulating layer over a GaN carrier. The report did not state the wafer diameter.
Why place GaN over an insulator and a carrier?
In conventional GaN epitaxy, the semiconductor layers are grown on a bulk substrate such as silicon, silicon carbide (SiC), or sapphire. With a transferred film, the active GaN surface and its support can be engineered more independently. In principle, that lets designers select the handle and bonding interface to suit requirements such as heat spreading, electrical isolation, mechanical support, or compatibility with a fabrication process, while retaining a GaN surface for device fabrication.
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That flexibility is an implication of the layer-transfer architecture, not a measured performance result from the 2005 demonstration. The available account does not establish that the structure improved device efficiency, thermal performance, yield, or cost.
How the work developed after 2005
Four- and six-inch engineered GaN wafers
In 2012, Soitec and Sumitomo Electric announced demonstrations of four-inch and six-inch engineered GaN substrates. Sumitomo supplied bulk free-standing GaN in Japan, and Soitec applied Smart Cut in France to make the engineered wafers. The companies described the substrates as having low defect density and a path to lower cost than bulk GaN; those are partner claims, not independent test results.
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SmartGaN development
Soitec’s 2023 SmartGaN material described a 200 mm wafer architecture: an optimized GaN epitaxial stack above a transferred GaN seed layer, supported by a customized silicon or non-silicon handle wafer. The bonding interface can be selected for electrical isolation or conduction. The company identifies RF and power devices as target applications.
- RF: Soitec lists 5G infrastructure, small cells, and handsets as targets. Its 2024 registration document describes the intended benefit as smaller, more efficient high-power components.
- Power: The company says SmartGaN is intended to support thicker GaN layers while reducing the risk of substrate breakage during thermal cycles. It presents the technology as a route toward circuits above 1,200 V, not as evidence that such devices are already in production.
Soitec’s 2024 results presentation forecast pilot production in 2027 for 1,200 V lateral SmartGaN applications and showed an RF roadmap for 5G/6G power amplifiers. The date is a company expectation, not confirmation that pilot production has begun, and the roadmap may change.
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What became of the original GaN-on-insulator demonstration?
The 2005 GaN-on-insulator report established a wafer-transfer demonstration, but it is not the same thing as today’s SmartGaN development. The later work uses related layer-transfer ideas in engineered GaN substrates and, in SmartGaN, combines a transferred GaN seed layer with an optimized epitaxial stack and a customizable handle wafer.
Soitec’s 2024 registration document describes current GaN-on-SiC and GaN-on-Si epitaxial-wafer lines and notes that the company presented SmartGaN development in 2023. This supports a continuing GaN substrate and development effort, but does not establish commercial availability, production volume, independent device performance, or the final outcome of the 2005 GaN-on-insulator structure itself.
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What to compare when evaluating GaN substrate approaches
A substrate choice depends on the device and manufacturing requirements; the 2005 transfer demonstration alone does not show that an engineered wafer is preferable in every case. Compare options across these factors:
- Support material: silicon, SiC, sapphire, or an engineered handle wafer.
- Thermal and electrical behavior: heat-spreading needs, electrical isolation, and whether conduction through the bonding interface is desired.
- GaN layer quality: the quality of a transferred single-crystal layer and the quality of the epitaxial growth must both be considered.
- Wafer size and fab compatibility: SmartGaN is specified at 200 mm; Soitec describes CMOS-fab compatibility for the material.
- Device target: RF power amplifiers for 5G/6G and power devices have different requirements.
- Manufacturing maturity and cost: assess production status, wafer supply, yield, donor-wafer reuse, and demonstrated—not merely projected—cost.
At the time of the 2005 report, Picogiga International chief operating officer Jean-Luc Ledys described the effort as part of a broader strategy: “This GaN capability is a part of our roadmap strategy to develop and supply advanced engineered substrates for compound semiconductors for a variety of applications.”
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