Shunt-capacitance compensation stabilizes an amplifier by adding a capacitor in parallel with the capacitance at a high-impedance internal node. The added capacitance lowers that node’s pole frequency so it becomes dominant, forcing loop crossover to occur with less phase lag. The trade-off is substantial: bandwidth, settling speed, slew rate, and full-power response can all fall sharply. The method is useful for understanding and deliberately slowing simple amplifiers, but integrated op amps usually obtain the same pole-sh rendahering effect more efficiently with Miller compensation.
Why an op amp needs frequency compensation
An amplifier with several gain stages normally has several poles. Each pole adds phase lag; if the feedback loop reaches unity gain after too much lag, the circuit can peak, ring, take a long time to settle, or oscillate.
Stability is determined by loop gain, not by open-loop gain alone:
T(jω) = A(jω)β(jω)
Here A is the amplifier’s open-loop response and β is the feedback factor. At the frequency where |T| = 1, phase margin indicates how far the loop is from the oscillation condition. Closed-loop gain changes β (and, equivalently, noise gain), so one op amp can be stable in one configuration and marginal in another.
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For a simplified two-pole amplifier, the usual objective is to make the first pole dominant. The gain then falls at roughly −20 dB per decade before the second pole contributes significant additional phase lag.
What shunt-capacitance compensation does
In this technique, a capacitor is connected in parallel with the existing capacitance at the lowest-frequency, high-impedance node. In a small-signal model that node has resistance R1 and capacitance C1. The compensation capacitor CC is added from the same node to the appropriate AC reference.
It is not generally a capacitor “across the op amp.” The exact node and reference depend on the amplifier topology; a textbook connection to ground is only a simplified model.
The node time constant becomes:
τ1 = R1(C1 + CC)
and its pole moves to:
f1,new = 1/[2πR1(C1 + CC)]
Because the pole is lower, loop crossover normally moves lower as well. That can increase phase margin and reduce closed-loop peaking, provided no other pole or zero becomes dominant first.
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How to calculate an initial capacitor
- Choose a target crossover frequency. Relate it to the required closed-loop gain, feedback factor, load, and desired transient response.
- Estimate the required dominant pole. A common two-pole starting point is f1,new ≈ fX/A0, where A0 is low-frequency open-loop gain as a voltage ratio.
- Calculate total capacitance at the node. Ctotal = 1/(2πR1f1,new).
- Subtract the capacitance already present. CC = 1/(2πR1f1,new) − C1.
- Verify the complete loop. The equation is an estimate; parasitic capacitances, output poles, feedback-network capacitance, and load effects determine the real result.
A steeper gain slope near crossover means less phase margin. In the simplified example, a −30 dB-per-decade rate of closure corresponds to about 45° phase margin. Real amplifiers can differ substantially because of extra poles, zeros, output impedance, and nonlinear behavior. TI discusses practical phase-margin targets in the approximate 45°–90° range, selected according to overshoot, settling, and tolerance requirements (TI stability and PSpice workflow).
Worked model example
The following values are from the illustrative two-pole model in All About Circuits’ shunt-capacitance example; they are not universal op-amp recommendations.
| Model result | Illustrative value |
|---|---|
| Uncompensated open-loop pole | Approximately 6.366 kHz |
| Chosen compensated first pole | Approximately 2.546 Hz |
| Calculated shunt capacitor | Approximately 62.51 nF |
| Alternative higher-phase-margin capacitor | Approximately 137 nF, producing about 65.5° in that model |
The dramatic movement from kilohertz to a few hertz demonstrates the central compromise: the model gains a more nearly single-pole response by becoming extremely slow. Increasing capacitance further can improve the modeled margin, but it also lowers crossover and lengthens settling.
Benefits and penalties
| Effect | What to expect |
|---|---|
| Stability | Lower crossover and a more dominant first pole can reduce peaking and ringing. |
| Bandwidth | Open-loop and closed-loop bandwidth generally decrease. |
| Transient response | Settling becomes slower; excessive capacitance can add substantial delay. |
| Slew rate | Often decreases approximately as compensation capacitance increases in architectures whose internal current charges that capacitor; bias current and current limiting also matter. |
| Full-power bandwidth | Falls when slew rate is reduced. |
| Implementation | Large capacitors consume significant integrated-circuit area and may require considerable transient current. |
“Stable” is therefore not the same as “good.” A capacitor that eliminates ringing but makes the required signal bandwidth impossible is not a successful design.
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Shunt capacitance versus Miller compensation
Miller compensation connects a capacitor across a gain stage, commonly from the output of a later stage back to an earlier high-impedance node. Voltage gain multiplies the capacitance seen at the input of that stage:
CM ≈ (1 + |Av|)CF
That multiplication produces pole splitting with a much smaller physical capacitor. In the cited comparison, a 9.90 pF Miller capacitor and a stage gain of roughly 250 produce about 2.485 nF of effective capacitance (Miller compensation explanation).
| Method | Capacitor location | Main advantage | Main limitation |
|---|---|---|---|
| Shunt capacitance | Parallel with capacitance at an internal high-impedance node | Simple dominant-pole calculation | Often requires a physically large capacitor and sacrifices speed |
| Miller compensation | Across an internal gain stage | High effective capacitance from a small component; practical for ICs | Can introduce a right-half-plane zero, slew-rate limits, and architecture-dependent stability |
Miller compensation is not automatically superior. Designers may need a nulling resistor or another network to control its zero, and its behavior depends on transconductance, stage gain, load, and bias conditions.
Do not confuse internal shunt compensation with capacitive-load compensation
Internal-node compensation changes the op amp’s open-loop poles. Capacitive-load compensation addresses an external capacitor connected to the output, such as a cable, ADC input, MOSFET gate, sensor, or display. Output resistance interacting with that load can add phase lag and cause oscillation.
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| Method | Primary location | Typical use | Trade-off |
|---|---|---|---|
| Shunt capacitance | Internal high-impedance node | Create a dominant pole | Large bandwidth and speed loss |
| Isolation resistor | Series with the output load | Decouple an op amp from a capacitive load | Output-voltage drop, output impedance, and power dissipation |
| Feedback-capacitor or in-the-loop network | Feedback path around the load | Shape loop gain while preserving load drive | Gain and bandwidth become network-dependent |
| RC snubber | Across or near the load | Damp a resonance | Requires tuning and dissipates energy |
TI identifies a series isolation resistor as one of the simplest output-load remedies (TI capacitive-load stability article). Analog Devices describes in-the-loop approaches that combine output isolation with a feedback capacitor (Analog Devices capacitive-loading techniques). Adding a capacitor at an op-amp output is not automatically compensation; it may be the destabilizing load.
A practical SPICE and bench workflow
- Choose a realistic model. Use a manufacturer macromodel or transistor-level model. An ideal voltage-controlled source with zero output impedance cannot reproduce output poles or capacitive-load interaction.
- List every capacitance. Include intentional compensation, transistor parasitics, input and feedback capacitance, package and PCB parasitics, load, cable, probe, ADC, sensor, or gate capacitance.
- Build a pseudo-open-loop test. Preserve the actual feedback factor while breaking the loop in a controlled way.
- Run an AC sweep. Record unity-gain crossover, phase margin, gain margin, rate of closure, and closed-loop peaking. TI’s PSpice-for-TI guidance uses this measurement-driven workflow.
- Add the calculated capacitor and repeat. Sweep its value rather than assuming the hand result is final.
- Run a transient step. Check overshoot, ringing frequency, undershoot, and settling time.
- Test corners. Repeat across closed-loop gain, load, supply, temperature, component tolerance, and model corners.
- Bench-test the actual hardware. Probe and cable capacitance can create a failure or hide one; verify with the intended load and measurement setup.
A 45° phase margin is a common practical target associated with roughly 25% small-signal overshoot in one TI example, but it is not a universal specification (TI forum discussion).
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Common failure modes
Wrong node
A capacitor on a low-impedance or incorrect node can create an unwanted pole, increase noise, disturb biasing, or reduce phase margin instead of creating a dominant pole.
Capacitor too small
The second pole still contributes near crossover, producing gain peaking, ringing, or marginal stability.
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Capacitor too large
The amplifier may be well behaved but unusably slow, with low bandwidth, long settling, and poor full-power response.
Unity-gain stability overlooked
A value selected for a higher minimum closed-loop gain may fail at unity gain. Conversely, a unity-gain-stable design may be unnecessarily slow when used at high gain.
Open-loop response measured instead of loop gain
Only the complete loop, including β, load, feedback network, and parasitic paths, determines the relevant crossover and phase margin.
Current and tolerance ignored
Charging a large capacitor demands transient current. Capacitance, transconductance, load, supply, and temperature variation can move the poles enough to erase nominal margin.
When this technique makes sense
- Teaching dominant-pole compensation and two-pole Bode analysis.
- Experimenting with a discrete or deliberately slow amplifier where capacitor size is acceptable.
- Creating a conservative low-bandwidth loop while diagnosing an instability.
- Providing a first estimate before a transistor-level or macromodel simulation.
It is usually the wrong first choice for a compact, high-speed integrated op amp. Miller, feedforward, nested, or load-compensation architectures can obtain better speed-area trade-offs, while an output isolation network is more appropriate when the actual problem is a capacitive load.
Design checklist
- Have you identified the correct high-impedance node and its AC reference?
- What resistance and existing capacitance does that node present?
- What crossover frequency and minimum closed-loop gain are required?
- Is the op amp already internally compensated?
- Is the observed capacitor actually an external load?
- What phase margin, overshoot, settling time, and bandwidth does the application require?
- Have feedback, package, PCB, probe, and load capacitances been included?
- Have AC, transient, corner, and bench tests all been completed?
The Bottom Line
Shunt-capacitance compensation buys phase margin by lowering a high-impedance node’s pole, but it pays for that margin with bandwidth and speed. Use the RC calculation as a starting estimate, analyze the complete loop, and choose Miller or capacitive-load compensation instead when area, settling time, or output-drive performance matters.
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