On May 2, 2024, Synopsys announced that Samsung Electronics had completed the production tape-out of a high-performance mobile system-on-chip (SoC) using Samsung Foundry’s Gate-All-Around (GAA) process technology. The unnamed design includes flagship CPU and GPU designs. Synopsys says its AI-driven design tools helped achieve 300 MHz higher performance than alternative implementation approaches and 10% lower dynamic power—but the announcement does not identify the exact Samsung process variant, a phone that will use the chip, or any consumer benchmark.
What Samsung actually taped out
The announcement describes a mobile SoC, not just a standalone CPU core. Samsung System LSI developed a design containing flagship CPU and GPU architectures, with Synopsys tools and IP used in the design flow. It was the first production tape-out of this kind that the companies publicly announced on Samsung Foundry GAA technology, according to Synopsys’ May 2, 2024 release.
The release did not name the SoC or give it an Exynos model number. Calling it an Exynos chip, identifying its CPU or GPU designs, or assigning it to a particular Galaxy device would go beyond what the announcement confirms.
What “3nm” means here
Synopsys’ official announcement identifies Samsung Foundry’s advanced GAA process technology but does not name an exact process designation. Contemporary coverage commonly described the design as 3nm-class; AnandTech’s contemporaneous reporting discussed SF3 and SF3E as possibilities while noting that Samsung had not disclosed the exact node. “3nm-class” is therefore a useful description of the reported generation, not confirmation that this chip used SF3, SF3E, or another specific variant.
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Modern node labels are technology-generation names. They are not literal measurements of every transistor feature, nor do they guarantee a particular transistor density, speed, or power consumption. Differences between process revisions can matter: implementation rules, design libraries, operating targets, manufacturing readiness, and yield all affect what a chip can achieve.
Why GAA matters
In a FinFET transistor, the gate controls the channel from three sides. A Gate-All-Around design surrounds the channel more completely, giving the gate greater electrostatic control. That can help process designers manage leakage and pursue performance or power improvements.
GAA is not an automatic performance upgrade for every chip. Results depend on the specific process implementation and the design’s libraries, voltage and frequency targets, physical layout, and manufacturing results. The announcement establishes that the SoC was designed on Samsung Foundry GAA technology; by itself, it does not prove a measured advantage over a comparable FinFET chip.
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Why this was a meaningful milestone
The news was more specific than Samsung having a 3nm-class foundry process: it showed a complex mobile application-processor design reaching production tape-out on the company’s GAA technology. A contemporaneous report carried by Inkl placed the milestone in the context of earlier Samsung 3nm-class GAA products, which it described as less complex than a flagship smartphone application processor. That context is the report’s characterization, rather than a new product claim in Synopsys’ announcement.
For Samsung, the design milestone is relevant to its ability to build advanced mobile chips on its own foundry process. For Synopsys, it is a customer example of AI-assisted electronic-design automation (EDA) being used in a demanding physical-design flow. Neither point, without evidence about manufacturing and a shipped product, establishes commercial success or a consumer-facing improvement.
What the Synopsys tools contributed
EDA software helps engineers turn a chip’s functional description into a physical layout that can be manufactured. The Synopsys release names Synopsys.ai, Fusion Compiler, DSO.ai, and Synopsys IP in the flow. In practical terms, the tools assisted engineers in implementing and optimizing a design; they did not independently invent and validate a complete smartphone processor.
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Fusion Compiler: implementation from RTL to layout
Fusion Compiler is Synopsys’ RTL-to-GDSII implementation tool. RTL, or register-transfer-level code, describes digital logic. GDSII is a file format used to represent the physical layout sent toward manufacturing. The implementation work between them includes arranging logic and routing its connections while meeting constraints such as timing, area, and power.
DSO.ai: searching implementation choices
DSO.ai uses AI-driven design-space optimization to explore implementation choices against goals such as performance, power, and area. Instead of relying only on engineers to iterate manually through alternatives, an optimization tool can search many combinations of settings and approaches. The useful result still depends on the objectives, constraints, libraries, and models supplied to it, and on engineers checking the resulting design.
Physical-design techniques cited
Synopsys also cited design-partitioning optimization, multi-source clock-tree synthesis (MSCTS), advanced wire optimization to reduce crosstalk, and a virtual-flat hierarchical implementation approach. These address different physical-design challenges: partitioning organizes work on a large design; clock-tree synthesis distributes timing signals; wire optimization addresses interconnect effects; and hierarchical methods structure implementation across blocks without treating each one as an entirely isolated problem.
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At advanced process generations, such choices interact. A change that improves timing may increase power, congestion, or routing complexity. AI-assisted EDA is best understood here as an optimization and productivity tool within an engineer-directed design flow—not as a substitute for chip architecture, verification, process technology, or fabrication.
How to interpret the performance and power claims
The figures below are claims attributed to the companies in the Synopsys announcement, not independent measurements of a shipping chip.
| Claim | What the announcement says | What it does not establish |
|---|---|---|
| Performance | The design achieved 300 MHz higher performance than “alternative approaches.” | The release does not provide the baseline design, clock frequency, voltage, workload, or a comparison with an earlier Exynos processor. |
| Dynamic power | The design achieved 10% lower dynamic power. | The release does not provide the comparison conditions. This is not a claim of 10% lower total SoC power or 10% longer phone battery life. |
| Design effort | Synopsys and Samsung reported saving weeks of manual design effort. | The announcement does not detail the measurement method or independently substantiate the time saved. |
| Power, performance, and area | The release describes the result as having leading or highest performance, power, and area characteristics. | Without published measurements and a defined comparison set, this remains a company claim, not an independent industry ranking. |
Dynamic power is the power associated with circuit activity, such as switching signals. A phone’s total power use also involves factors such as leakage, memory, display, modem, workload, software scheduling, and thermal behavior. Battery life is a property of the entire device and its use, not a direct conversion of a single chip-level dynamic-power figure.
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What tape-out means—and what comes next
Tape-out is a major design milestone: the completed layout is released for manufacturing. It does not mean that a finished processor has been made, validated, qualified for reliable production, or shipped in a phone.
- Design signoff: Engineers complete the required checks on the final design before release. The announcement confirms a production tape-out, but does not publish detailed signoff results.
- Mask preparation and wafer fabrication: The design is prepared for manufacturing and wafers are processed. The announcement does not establish when or whether this unnamed design entered wafer production.
- Wafer sort and characterization: Individual dies are tested and their electrical behavior assessed. No results for this SoC were included in the release.
- Packaging and system validation: Dies are packaged and evaluated in a broader system, including hardware and software. No product-validation results were announced.
- Reliability, yield, and product qualification: A commercially viable product must meet requirements for reliable operation and manufacturable yield. The announcement provides no yield or qualification data.
- Integration and release: A customer or Samsung product team would integrate a qualified chip into a product before mass production and launch. No device, launch date, or consumer availability was confirmed.
What remains unknown
- The SoC’s product name and whether it will be sold as an Exynos model.
- The exact Samsung process designation, including whether it was SF3, SF3E, or another variant.
- The identities of the CPU and GPU designs, as well as the chip’s clock targets, die size, and transistor count.
- Wafer yield, production volume, cost, and whether the design entered mass production.
- Any Galaxy model or other device intended to use it, or a shipping schedule.
- Independent performance, gaming, AI, thermal, or battery-life results.
What this says about Samsung Foundry—and what it does not
The tape-out is evidence of a complex mobile SoC design milestone on Samsung Foundry GAA technology, with Synopsys tools supporting implementation. It does not establish that Samsung Foundry has beaten TSMC: the announcement offers no apples-to-apples comparison of process density, yield, cost, total power, or shipping-product performance.
Assessing the commercial significance would require evidence beyond tape-out: how the design performs after fabrication, whether it meets reliability and yield targets, whether it can be produced at viable cost and scale, and whether it is integrated into a product whose real-world behavior can be measured.
Bottom line
Samsung and Synopsys announced a substantial design milestone: an unnamed flagship-class mobile SoC reached production tape-out on Samsung Foundry GAA technology using Synopsys’ AI-assisted EDA flow. The 300 MHz and 10% dynamic-power figures describe company-reported design comparisons, not verified gains for a shipping processor or phone. Until Samsung identifies the chip and reports manufacturing, validation, or product results, the announcement is strongest as evidence of design-flow capability—not proof of a faster or longer-lasting Galaxy device.
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