SemiDynamics described its 64-bit RISC-V core family as the “first fully configurable” processor core when it introduced the family in April 2023. That is the company’s launch claim, not an independently established industry-wide first. The key distinction is what the company meant by configurable: not merely selecting options from a fixed menu, but having SemiDynamics engineers customize processor blocks for a particular customer.
What did SemiDynamics mean by “fully configurable”?
Configurability can mean different things in processor IP. In a narrower sense, a customer chooses among options already exposed by a design, such as cache size, address-bus width, or supported interfaces. SemiDynamics’ pitch went further: customer-specific engineering could alter sophisticated parts of a core to meet a design’s needs.
Founder and CEO Roger Espasa described the model this way: “We do the customization for the customer rather than expecting the customer to do it themselves.” The distinction is therefore not simply whether a core can be configured, but who makes the changes and how deeply they can reach into the design. Embedded.com’s April 19, 2023 article presents this as SemiDynamics’ approach; it does not survey or verify every RISC-V supplier.
What kinds of changes were described?
The article discussed customer-specific changes such as adding instructions, creating separate address spaces, and introducing new memory-access capabilities. Those are examples of changes to processor behavior and architecture, rather than simple selections from a predefined set of parameters.
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The practical boundary matters. Changing a cache setting is not equivalent in scope to changing an instruction set extension or how memory is accessed. Nor does the label alone establish which blocks a supplier will modify for a given customer. Buyers would need to establish that against the supplier’s technical documentation and a specific project proposal.
What was Atrevido?
Atrevido was the first named member of SemiDynamics’ core family in the 2023 coverage. That article reported out-of-order scheduling, memory management unit (MMU) support, Linux readiness, cache-coherent multiprocessor support, and support for RISC-V Vector Specification 1.0. These are historical, vendor-reported feature descriptions, not independent validation of an implementation or its performance. The original article provides the launch-era account.
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The RISC-V instruction-set architecture (ISA) and a particular commercial processor core are related but distinct. The ISA specifies the software-visible instruction architecture; the core is an implementation that may add or customize features within the applicable rules. For ratified ISA documents, consult RISC-V International’s ratified specifications. Core-specific behavior and available customization require documentation from the core supplier.
How should a buyer evaluate a configurable core?
“Fully configurable” is not a standardized guarantee of unlimited changes. A useful evaluation should pin down what is actually adjustable, who performs the engineering, and what the customer receives.
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- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
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- Customer controls: Ask which settings customers select themselves and which changes require vendor engineering.
- Depth of customization: Identify whether modifications can reach complex blocks such as the out-of-order scheduler, vector unit, or coherency engine, rather than only peripheral parameters.
- Integration and verification: Establish how responsibilities for integrating and verifying a customized design are divided between the supplier and customer.
- Design goals: Define the project’s power, performance, and area priorities, then ask how proposed changes address them. The available launch coverage does not supply comparable benchmarks or a methodology for assessing performance claims.
Does the “first” claim establish industry priority?
No. SemiDynamics used the “first fully configurable” description at launch, while the Embedded.com article itself noted that other processors had also been called fully configurable and that the answer depends on the definition. The reviewed coverage does not independently establish that no other vendor offered equivalent customization. Treat “first” as the company’s attributed claim, not a settled market-wide fact.
SemiDynamics’ newsroom index later included coverage of a Configurator tool, indicating that the company continued to present customization as part of its offering. A company newsroom is vendor material, however, not a substitute for current technical documentation or independent verification. SemiDynamics’ newsroom index is the source for that later context.
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