NEC announced a dedicated FPGA edition of its CyberWorkBench design environment on August 25, 2011. The software lets engineers describe hardware functions in C or SystemC and synthesize them into FPGA circuits, with integrated simulation, debugging, and verification—an alternative to beginning with Verilog or VHDL.
What NEC announced in August 2011
NEC said it had begun selling CyberWorkBench FPGA専用版, a version of its high-level synthesis and verification environment tailored to FPGA development. NEC’s announcement described work with FPGA makers Altera and Xilinx to optimize designs for device-specific resources and routing characteristics. Its synthesis engine could target resources such as DSP and memory blocks, and the interface was simplified for software developers and people new to LSI design. NEC’s August 25, 2011 announcement introduced three editions:
| Edition | FPGA support and scale | Published price |
|---|---|---|
| Professional | Supports all FPGA devices. | Not stated in NEC’s 2011 announcement. |
| Standard | Limits supported FPGA families and circuit scale. | Not stated in NEC’s 2011 announcement. |
| Basic | Limits supported FPGA families and circuit scale. | Starts at ¥2,000,000 before tax, as listed by NEC in 2011. |
The announcement describes a product lineup and launch pricing, not current availability or current prices.
How C-to-FPGA design works in CyberWorkBench
CyberWorkBench uses high-level synthesis: engineers describe a function in ANSI C or SystemC, verify and debug that description, then synthesize it into hardware. The result is a hardware circuit, not a program that runs on a general-purpose CPU. The approach does not eliminate HDL from an FPGA project; it changes the abstraction level at which the design can begin. Generated hardware can still be represented and integrated through standard hardware-design flows.
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- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
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NEC characterizes CyberWorkBench as a “C-based High Level Synthesis and Verification tool suite both for ASIC and FPGA” on its product page. Its FPGA-specific edition focused on device-aware optimization, while the broader CyberWorkBench suite was described for both ASIC and FPGA work. Verification capabilities included simulation, debugging, and property checking; NEC’s later description also refers to dynamic and static verification.
What NEC claimed about productivity
NEC’s 2011 comparison put the design-description volume at about one-seventh that of its comparison approach and said simulation could be up to several hundred times faster than RTL simulation. These are NEC’s own stated comparisons, not independent benchmark results. The ratios describe particular comparisons and should not be treated as guaranteed gains for every design, device, or workflow. NEC’s launch release contains the original comparison.
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
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- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Later NEC announcements reported customer outcomes in distinct projects. They offer examples of where the approach was used, but they do not establish a universal productivity multiplier:
- Communication control: In 2017 NEC said Taiwan fabless IC vendor Faraday Technology used CyberWorkBench to design communication-control FPGA hardware as an ASIC prototype. NEC reported one-sixth the design effort versus manual circuit conversion and said the tool had been introduced at more than 100 manufacturing companies since its 2006 launch. NEC’s Faraday announcement is the source for those figures.
- Medical-device control: In 2014 NEC said Terumo used CyberWorkBench for the control LSI of an infusion-management medical device and achieved a design period about 60% shorter than with manual synthesis. This is NEC’s report of that project, not a general product benchmark. NEC’s Terumo announcement describes the use case.
- Data-processing hardware: In 2012 NEC reported a SQL-to-FPGA technique using CyberWorkBench that reduced a stated hardware-design period from months to hours, approximately one-fiftieth of the previous time. The same release claimed processing could be changed dynamically without shutting down the system. NEC’s announcement provides the project details.
What the FPGA edition means for an engineering team
The main distinction is the input model. In an HDL-first workflow, engineers directly describe hardware in Verilog or VHDL. With CyberWorkBench, they can describe functions at a higher level in C or SystemC, then use synthesis and verification tools to produce hardware. This can be especially relevant when software-oriented engineers are involved or when functional behavior is easier to express in C.
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High-level synthesis does not remove the need to reason about hardware constraints. The synthesized result still has to meet the target device’s area, timing, and resource requirements. NEC’s product positioning emphasizes optimization for FPGA resources and device families; the edition limits also indicate that supported families and circuit scale varied by license tier. Teams considering such a workflow would need to evaluate the resulting hardware and its fit for their target device rather than assuming that a shorter source description automatically yields a smaller or faster circuit.
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