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Announced on January 16, 2024, Microchip’s LAN9694, LAN9696 and LAN9698 are industrial Ethernet switch chips designed to scale from lower- to higher-capacity managed networks. All three combine multi-rate Ethernet interfaces with an integrated 1 GHz Arm Cortex-A53 processor; TSN features are available in designated variants, while HSR/PRP redundancy is reserved for RED variants. The practical choice depends as much on network timing, redundancy and external interface hardware as on the headline bandwidth.
What Microchip announced
Microchip introduced the LAN9694, LAN9696 and LAN9698 as a scalable family for industrial and process automation, transportation, power-grid and substation networks, and ring or intra-ring topologies. The chips pair managed switching with processing and networking features intended for embedded equipment rather than plug-and-play consumer switches. Microchip’s January 16, 2024 announcement describes the family and its TSN focus.
Microchip’s materials cite up to 30 ports, with interface configurations that can include 1 GbE, 2.5 GbE, 5 GbE and 10 GbE. That maximum port count is configuration-dependent; it does not mean every port can run at 10 GbE simultaneously. The family brief also describes Ethernet rates from 10 Mbps through 10 Gbps. The product brief and current product pages should be checked for the exact device and interface configuration.
How the LAN9694, LAN9696 and LAN9698 compare
| Device | Bandwidth figure in Microchip materials | Port and interface capabilities | TSN and redundancy variants | Package and temperature designation |
|---|---|---|---|---|
| LAN9694 | 46G in the family brief and announcement; 48G in the current product-page designation | Configurations vary; family supports 1G, 2.5G, 5G and 10G interfaces, up to 30 ports | Standard, TSN and RED variants; HSR/PRP in RED variants | 356-ball, 17 × 17 mm FCBGA; standard designation 0°C to +105°C, TSN/RED designation −40°C to +110°C |
| LAN9696 | 66G | Configurations vary; family supports 1G, 2.5G, 5G and 10G interfaces, up to 30 ports | Standard, TSN and RED variants; HSR/PRP in RED variants | 356-ball, 17 × 17 mm FCBGA; standard designation 0°C to +105°C, TSN/RED designation −40°C to +110°C |
| LAN9698 | 102G | Configurations vary; family supports 1G, 2.5G, 5G and 10G interfaces, up to 30 ports | Standard, TSN and RED variants; HSR/PRP in RED variants | 356-ball, 17 × 17 mm FCBGA; standard designation 0°C to +105°C, TSN/RED designation −40°C to +110°C |
The 46G/48G LAN9694 discrepancy is in Microchip’s own materials: the product-identification table in the family brief gives 46G, while the current LAN9694 product page calls it a 48G switch. Treat either number as a document-specific designation, not as a promise of application throughput. The brief’s temperature figures are product-identification designations; consult the selected ordering code’s current datasheet for the precise ambient and junction limits rather than interpreting them as interchangeable operating-temperature specifications.
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“Standard,” “TSN” and “RED” refer to feature variants, not just descriptions of the same chip. The TSN variants add time-sensitive networking functions. RED variants add HSR/PRP redundancy on top of TSN. Confirm features against the exact ordering code and software configuration before freezing a design.
What TSN adds—and what it does not
Time-Sensitive Networking (TSN) is a family of IEEE Ethernet standards and mechanisms. It can help a network deliver scheduled, bounded-latency traffic alongside ordinary best-effort Ethernet, but it is not a single switch mode that automatically makes all traffic deterministic.
- IEEE 802.1Qbv, Time-Aware Shaper: schedules transmission opportunities for traffic queues.
- IEEE 802.1Qch, Cyclic Queuing and Forwarding: coordinates traffic forwarding in cycles to support predictable delivery.
- IEEE 802.1Qci, Per-Stream Filtering and Policing: identifies and constrains streams to limit the effect of misbehaving traffic.
- IEEE 802.1AS-2020: provides timing and synchronization mechanisms for participating network devices.
- IEEE 802.1CB: supports frame replication and elimination for reliability (FRER).
- IEEE 802.1Qbu and IEEE 802.3br: support frame preemption, allowing selected express traffic to interrupt eligible lower-priority frames.
Microchip also lists cut-through switching and enhanced scheduling among the family’s capabilities. In a factory, a properly configured system could schedule time-critical motion-control traffic while carrying diagnostics and less time-sensitive data on the same Ethernet infrastructure. That outcome depends on synchronized clocks, traffic classification, queue and gate settings, bandwidth planning, compatible endpoints and the network’s configuration or control software. A TSN-capable switch can still carry conventional best-effort traffic, and its presence alone does not establish end-to-end latency guarantees. See the LAN9694 product information for Microchip’s listed functions.
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HSR, PRP and other redundancy options
HSR: duplicate traffic around a ring
High-availability Seamless Redundancy (HSR) sends duplicate frames along two directions, commonly around a ring. A receiving node uses the first valid copy. With a suitable topology and compatible devices, a single path failure can be handled without waiting for conventional network reconvergence.
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PRP: duplicate traffic over two networks
Parallel Redundancy Protocol (PRP) sends duplicate frames through two independent local-area networks. It fits a design that maintains separate parallel networks rather than one ring. The additional path infrastructure and duplicated traffic have implications for cabling, equipment and capacity.
On this family, the RED variants are the ones identified for TSN plus HSR/PRP; do not assume every standard or TSN-only ordering code provides HSR/PRP. Microchip’s family materials also list G.8031 Ethernet Linear Protection Switching, G.8032 Ethernet Ring Protection Switching, Media Redundancy Protocol (MRP), FRER, ODVA Device Level Ring and Media Redundancy with Planned Duplication. These are related availability or protection mechanisms, not interchangeable guarantees; confirm support for the specific part, protocol combination and software release in the current documentation. The family product brief describes the documented capabilities.
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Interfaces, processing and board-level implications
Multi-rate interfaces need system design
Depending on the device interface description and configuration, the family lists RGMII, SGMII, QSGMII, USGMII, USXGMII and XFI, as well as 100FX, 1000X and SFI support. These interface names describe ways to connect the switch to physical-layer devices or other system components; they do not mean the chip has an integrated copper PHY for every port.
Microchip’s current LAN9694 page says “Copper Support: No.” A design using copper Ethernet therefore needs appropriate external PHYs, and a design using optical links must account for its optical interface components. Both approaches affect component cost, power, clocking, signal integrity, magnetics where applicable, EMI/EMC behavior and validation. The board designer must also plan SerDes routing and the chosen PHY or module connections.
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Each device includes a 1 GHz single-core Arm Cortex-A53. Family materials also list a DDR3/DDR4 SDRAM controller, a PCIe 2.0/3.0 CPU interface, QSPI flash and internal ECC SRAM. The switch provides managed Layer 2 switching, Layer 3 forwarding and routing features, VLAN and QoS processing, and content-aware processing through Microchip’s VCAP technology. TrustZone and Arm Trusted Firmware-related capabilities support security functions, including secure-boot-related features.
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The integrated processor can support a managed-switch system without necessarily adding a separate management CPU, but it does not make the chip a self-contained network appliance. A product still needs an appropriate memory and boot-storage design, power and clock circuitry, board-support software, firmware integration and security provisioning. An external host may remain preferable when a product already has a central processor or needs stronger software separation. Security features are components of a security design, not a guarantee that the complete product is secure.
Which LAN969x variant should you consider?
| Design need | Starting point | Reason and qualification |
|---|---|---|
| Managed industrial switching without a requirement for TSN or HSR/PRP | Standard LAN969x variant | Avoids selecting time-sensitive or seamless-redundancy features that the application does not need; check other required protocols against the exact variant. |
| Scheduled traffic, synchronization, policing or preemption | LAN969xTSN | Provides the relevant TSN feature set, but end-to-end behavior still requires network-wide engineering and compatible endpoints. |
| TSN plus HSR/PRP | LAN969xRED | RED variants add HSR/PRP redundancy; account for duplicate traffic and the required paths or networks. |
| Lower aggregate capacity is sufficient | LAN9694 | Lowest-capacity family member; verify the 46G/48G documentation discrepancy and actual interface allocation. |
| Intermediate capacity | LAN9696 | 66G designation positions it between the LAN9694 and LAN9698; confirm that the planned port mix fits. |
| Highest stated family capacity or demanding 10G mix | LAN9698 | 102G designation gives the family’s highest stated aggregate bandwidth, not a guarantee that all desired ports can saturate concurrently. |
Aggregate switching bandwidth is not the same as a guaranteed count of simultaneously saturated user ports or application throughput. Real results depend on port configuration and interface allocation, traffic direction, switching architecture, buffering and enabled features. Higher capacity can enable more high-speed links and traffic headroom, while also increasing SerDes, PCB signal-integrity, power, thermal, external-component and validation demands.
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Microchip lists VSC-family software packages associated with its switch architecture: VSC6819 WebStaX, VSC6817 IStaX and VSC6816 SMBStaX. The appropriate package, licensing, documentation access, operating mode and feature coverage for a selected LAN969x part should be confirmed with Microchip. Some resources may require a myMicrochip account or customer access.
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- VSC6819 WebStaX software page
- VSC6817 IStaX software page
- VSC6816 SMBStaX software page
- Microchip software-options application note
For development, Microchip lists the LAN969x 10 × 10G EVB (EV89P81A) and the LAN969x 24-port EVB (EV23X71A), described as 24 × 1G plus 4 × 10G Ethernet. Evaluation boards can help assess software, switching and interface behavior, but their configuration should not be treated as the production chip’s complete port specification or as representative of a final product’s cost, size, power or regulatory design.
Design checks before choosing a part
- Define the traffic and topology: estimate port speeds and traffic patterns, then decide whether ordinary managed switching, TSN scheduling or a specific redundancy method is needed.
- Verify the exact ordering code: distinguish standard, TSN and RED features, and check temperature and protocol support in the current datasheet.
- Plan the physical layer: select external PHYs or optical components and budget their board area, power, clocks, signal-integrity and compliance work.
- Plan TSN as a network system: establish clock synchronization, stream classification, scheduling and endpoint compatibility before assuming deterministic behavior.
- Validate software access early: confirm the needed software package, license, documentation and support path with Microchip.
- Use sales channels for availability: a product page marked “In Production” does not establish current distributor stock, lead time or volume availability.
For a lower-speed design that needs TSN but not the LAN969x family’s multi-gigabit interfaces, Microchip’s switch portfolio also includes the LAN9662 and LAN9668. Their suitability depends on the required interfaces and feature set; compare them using Microchip’s Ethernet-switch portfolio information rather than assuming they are direct substitutes.
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