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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchLattice’s first FPGA built on fully depleted silicon-on-insulator (FD-SOI) was CrossLink-NX, introduced on December 10, 2019. It was the first FPGA family on the company’s Nexus platform, which pairs Lattice’s FPGA fabric with Samsung’s 28 nm FD-SOI process.
What Lattice announced
Lattice introduced the Nexus platform on December 10, 2019, naming CrossLink-NX as its first Nexus FPGA family. The announcement made CrossLink-NX the first Lattice FPGA built using Samsung’s 28 nm FD-SOI process. Lattice later described the launch as the first time FD-SOI technology had been brought to FPGAs in a technical article dated February 3, 2020. Lattice’s Nexus announcement and its technical article on FD-SOI provide the company’s account.
What Nexus and FD-SOI mean
Nexus is a platform combining a Lattice-designed FPGA fabric with Samsung’s 28 nm FD-SOI manufacturing process. FD-SOI is a silicon process technology; it does not change the fact that the device is a programmable FPGA. Lattice said the process has 50 percent lower transistor leakage than bulk CMOS and supports a low-power platform. That figure is the company’s claim, not an independent comparison in the launch material. Nexus also emphasized configurable power-performance trade-offs and fast configuration for systems that need to become operational quickly.
For a system designer, the practical point is the intended combination: programmable logic, a compact implementation and power-conscious operation. The process claim alone does not establish how much power a particular design will use; results depend on the device, configuration, workload and surrounding system.
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Why CrossLink-NX targeted embedded vision
Lattice positioned CrossLink-NX for embedded-vision and Edge AI systems that connect multiple image sensors, cameras and displays. Its stated strengths included MIPI interfaces, PCI Express support, small form factor and low power, along with a design-software and intellectual-property ecosystem. These features address tasks such as moving or bridging video streams between components; they do not by themselves guarantee a particular image-processing performance or system power figure.
Lattice claimed CrossLink-NX could deliver “up to 75 percent lower power compared to similar class competitive devices.” This is a vendor comparison, not an independently verified benchmark, and “up to” describes a claimed maximum rather than a result that every design should expect. In the launch announcement, Leopard Imaging co-founder and president Bill Pu said the FPGA’s low power, small size, interfaces and software/IP library helped the company develop video signal bridging, aggregation and splitting applications with one device. Lattice’s CrossLink-NX announcement contains the product positioning and customer quote.
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What followed CrossLink-NX
Lattice launched Certus-NX on June 24, 2020, as the second FPGA family on the Nexus platform. Where CrossLink-NX’s initial positioning centered on embedded vision, Certus-NX was presented for data processing, signal bridging and system control, with PCIe and Gigabit Ethernet support. Lattice claimed up to twice the I/O density per square millimeter versus similar competing FPGAs. As with the CrossLink-NX power figure, this is a vendor claim, not an independent measurement. Lattice’s Certus-NX announcement describes its intended applications and comparison.
Does Nexus have radiation tolerance for aerospace and defense?
In an August 23, 2021 release for the SEE/MAPLD workshop, Lattice said Nexus FPGAs manufactured with 28 nm FD-SOI demonstrate the total-ionizing-dose tolerance required for aerospace and defense applications. That is a relevant vendor statement, but the cited release does not include an independent test report or a complete radiation-data table. It therefore should not be treated as a substitute for radiation qualification evidence for a specific part and mission. Buyers evaluating a design for space or other radiation environments should request device-specific test data, qualification details and applicable limits from the manufacturer. Lattice’s workshop announcement describes its presentation.
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How to assess a Nexus FPGA for a design
CrossLink-NX is a plausible candidate when a design needs compact programmable logic to connect cameras, sensors and displays, particularly where MIPI or PCIe connectivity matters. Certus-NX is the more directly relevant family in the launch material for general-purpose data handling, signal bridging and system control with PCIe or Gigabit Ethernet. A product-family description is not enough to select a specific part: check the device-level resources, package, interface requirements and development support against the complete design.
Quick Recap
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- Altera Cyclone IV FPGA includes 6,000 Logic Elements with two clock multipliers. The Cyclone IV FPGA is the perfect balance of inexpensive cost versus plentiful logic cells, 20KBytes of SRAM, and General Purpose Input/Output pins. This is a great board to learn how to program FPGA's.
- Built in programmer cable allows configuring the FPGA with a single USB-C cable. The DPL can be powered from the USB cable or from the Barrel Connector. A separate JTAG header can also be used to program the FPGA using a compatible USB Blaster cable.
- 6x6 LED Array allows character and animations to be displayed at ultra fast speed. LED blocks can be individually turned on/off to allow LED signals to be used as I/O's
- 70 Inputs/Outputs originating at the FPGA are available at Stackable Headers organized around the edge of the board. The user can configure these I/O's using the FPGA project code.
- The DPL contains two oscillators, 66MHz and 100MHz. The 66MHz oscillator is used to provide clocking for the EPT ActiveHost USB communications core. The 100MHz oscillator can be used by the user clocked up using one of the onboard Clock-DLL modules.
- Interfaces: Confirm the exact MIPI, PCIe, Ethernet or other connectivity needed and whether the target device and package support it.
- Power: Treat Lattice’s platform and comparative power figures as vendor claims; estimate or measure power for the intended configuration and workload.
- Physical fit: Compare package dimensions and I/O availability with the board layout and connected components.
- Development: Check that the software tools, IP and development-board options support the required workflow and interfaces.
- Reliability: For aerospace, defense or other harsh environments, obtain device-specific qualification and radiation evidence appropriate to the application.
- System cost: Compare the full implementation, including FPGA, board, software/IP and validation work, rather than relying on a process-node or I/O-density claim alone.
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