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The wiring depends on the bus. With SPI, share clock and data lines but give each peripheral its own chip-select. With I²C, share SDA and SCL and assign every device a unique address. With RS-485, share a differential pair and use a protocol such as Modbus RTU to address one node at a time.

Master, slave and shared-bus basics

A master—also called a controller—starts transactions and commonly generates the clock. A slave, peripheral or target responds only when selected or addressed. Several devices can share conductors, but only the intended device may actively drive a shared return path at any instant.

The selection mechanism is bus-dependent: a physical chip-select line in SPI, an address in I²C, or a node identifier in Modbus. The term “master/slave” remains common in datasheets and searches; newer documentation may use controller/peripheral or controller/target.

SPI: one controller with several peripherals

SPI is usually the best fit for nearby devices when throughput and full-duplex transfers matter. It has no universal packet, register or acknowledgement format; each peripheral datasheet defines its command bytes, framing and timing. See TI’s overview at TI SPI overview.

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Independent chip-select wiring

                 +------------------ Peripheral 1
                 |       CS1 -------/
                 |
Controller       +------------------ Peripheral 2
SCLK  ------------------------------ SCLK
MOSI/COPI -------------------------- SDI
MISO/CIPO <------------------------- SDO
                 |
                 +------------------ Peripheral 3
                         CS3 -------/
Controller signal Peripheral 1 Peripheral 2 Peripheral 3
SCLK SCLK SCLK SCLK
MOSI/COPI SDI SDI SDI
MISO/CIPO SDO SDO SDO
CS1 CS input inactive inactive
CS2 inactive CS input inactive
CS3 inactive inactive CS input

MOSI/MISO are also called COPI/CIPO (controller out/peripheral in and controller in/peripheral out). All peripherals share SCLK and the controller-to-peripheral data line. A directly selected design normally needs one additional CS output for each peripheral, as described in TI’s multi-device SPI note.

Safe SPI transaction sequence

  1. Load that device’s clock polarity, clock phase, bit order, word length and maximum clock settings.
  2. Make every other CS inactive. Use pull resistors so CS lines cannot float during reset.
  3. Assert the selected CS.
  4. Send the device-specific command, register address and data; provide dummy bytes when its read protocol requires them.
  5. Observe setup, hold and inter-transfer delays.
  6. Deassert CS, then restore settings before selecting a peripheral with different requirements.

Only one CS should normally be active. The unselected devices must place MISO/CIPO in high impedance; verify this in each datasheet rather than assuming it. A device that keeps driving MISO needs a tri-state buffer, bus switch, separate controller or dedicated return path.

SPI modes and timing differences

Peripherals can require different CPOL/CPHA modes, bit order, idle levels, clock limits or CS polarity. Some require CS to stay low for an entire command-and-response frame; others reset their serial state machine when CS rises. NXP notes that controller settings may need to change between slaves: NXP SPI introduction.

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Daisy-chain SPI

Controller MOSI -> Peripheral 1 input
Peripheral 1 output -> Peripheral 2 input
Peripheral 2 output -> Peripheral 3 input
Peripheral 3 output -> Controller MISO
Controller CS ---------------- all peripherals
Controller SCLK -------------- all peripherals

A supported daisy chain saves CS pins, but every transfer shifts through every device. Frames become chain-length and bit-order dependent, a failed or unpowered device can interrupt the whole chain, and software must exchange one combined frame. It is not interchangeable with independent-CS wiring.

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When there are not enough CS pins

  • GPIO expander: Provides more outputs over I²C or SPI, but adds initialization, timing and reset-state dependencies.
  • Decoder/demultiplexer: A 2-to-4 or 3-to-8 decoder reduces GPIO use; check enable behavior, polarity and propagation delay.
  • SPI multiplexer or bus switch: Isolates non-tristating, powered-off or high-capacitance segments. TI describes these uses at TI SPI switch and multiplexer guidance.
  • Second SPI controller: Useful when devices need incompatible electrical or timing conditions.
  • Software CS: Ordinary GPIOs often give the most predictable control, especially when CS must transition between words.

Independent-CS pseudocode

void spi_read_device(uint8_t device, uint8_t *command, size_t command_len,
                     uint8_t *rx, size_t rx_len)
{
    deselect_all_devices();
    spi_set_mode(cfg[device].cpol, cfg[device].cpha);
    spi_set_bit_order(cfg[device].bit_order);
    spi_set_clock(cfg[device].max_clock_hz);
    cs_low(device);
    spi_write(command, command_len);
    spi_read(rx, rx_len);
    cs_high(device);
}

Add the delays, status polling, checksum or CRC, dummy bytes and timeout recovery required by the specific peripheral.

I²C: shared wires with addressed peripherals

I²C normally uses only SDA (bidirectional data) and SCL (clock). Outputs are open-drain or open-collector, so pull-up resistors create the high level and multiple devices can safely pull a line low. The NXP/TI copy of UM10204 defines addressing, pull-ups, clock stretching and nominal bus modes: I²C-bus specification and user manual.

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The controller sends a target address and read/write bit; only the addressed device acknowledges and participates. UM10204 lists Standard-mode up to 100 kbit/s, Fast-mode up to 400 kbit/s, Fast-mode Plus up to 1 Mbit/s and High-speed mode up to 3.4 Mbit/s. These are protocol-mode limits, not guarantees for a particular chip, cable or layout.

Address conflicts and electrical limits

  • Every active device needs a non-conflicting address. Two identical sensors with fixed addresses cannot be separated by changing a software byte.
  • Use an alternate address pin, I²C multiplexer, address translator or separate controller bus when addresses collide. A multiplexer creates isolated downstream channels; a translator changes the address seen on one segment.
  • Choose pull-ups for the total bus capacitance and required rise time. Device count and cable length are limited by capacitance, leakage and pull-up current.
  • Some devices stretch SCL by holding it low. The controller and driver must tolerate that behavior.

I²C read example

bool i2c_read(uint8_t address, uint8_t reg, uint8_t *buffer, size_t length)
{
    if (!i2c_start_write(address)) return false;
    if (!i2c_write_byte(reg)) return false;
    if (!i2c_restart_read(address)) return false;
    for (size_t i = 0; i < length; ++i)
        buffer[i] = i2c_read_byte(i == length - 1); // NACK final byte
    i2c_stop();
    return true;
}

SDKs differ in address representation, repeated-start support and timeout handling. A bus held low may require disabling the peripheral, manually toggling SCL, issuing a STOP-like sequence, reinitializing and resetting the offending device; use the MCU and device vendor’s prescribed recovery sequence.

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RS-485 and Modbus RTU

RS-485 is an electrical differential signaling layer, not a complete master/slave protocol. UART supplies bytes, while Modbus RTU supplies addressing, function codes, CRC and request/response rules. Other RS-485 systems may use DMX or proprietary framing.

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Master transceiver
        |
======== differential pair ========
   |                 |                 |
 Node 1            Node 2            Node 3
 unique ID         unique ID         unique ID

The controller polls one node, waits for its response, then polls the next. Only the addressed node should enable its driver. Follow the selected transceiver and Modbus guide for termination at the cable ends, biasing, cable topology, driver-enable timing and turnaround delays. Do not assume a universal node count; loading, data rate, cable and termination determine the limit.

Choosing the bus

Requirement SPI I²C RS-485/Modbus
Short-board throughput Strong Moderate Implementation-dependent
Fewest shared signal wires Needs CS lines Two Differential pair
Full duplex Yes Not typical Usually half-duplex
Long cable runs Poor without extra hardware Limited Strong
Addressed multidrop Physical CS Built-in addresses Protocol node IDs
Standardized packet format Device-specific Bus rules standardized Modbus provides one common option

Choose SPI for fast, nearby peripherals and sufficient CS resources; I²C for many low- to moderate-speed ICs sharing two PCB traces; and RS-485/Modbus for physically separated or industrial nodes.

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Worked design patterns

MCU with three SPI devices

Route SCLK, MOSI/COPI and MISO/CIPO to all three devices. Connect CS1, CS2 and CS3 to separate GPIOs, add inactive-state pulls, store a configuration record for each peripheral, and assert exactly one CS per transaction. Check every MISO output in the datasheets.

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Four I²C sensors with a duplicate address

Connect SDA and SCL to all sensors with correctly sized pull-ups. Give each sensor a distinct address where possible. If two remain identical, place one group behind an I²C multiplexer or on a separate bus; do not attempt to solve the conflict in software alone.

Several Modbus RTU nodes

Connect properly terminated RS-485 wiring, assign unique node IDs, configure identical serial settings, and poll sequentially. Control each transceiver’s driver-enable pin so only the master or the addressed responder transmits.

Troubleshooting checklist

No device responds

  • Confirm ground reference, voltage levels, power rails and connector pinout.
  • Check CS polarity and reset-state pulls for SPI, or address and pull-ups for I²C.
  • For Modbus, verify baud rate, parity, termination, node ID and CRC.

The first device works but adding a second fails

  • Look for overlapping CS assertions or incorrect CS wiring.
  • Check MISO contention and whether the second device needs a different CPOL/CPHA, clock limit or CS delay.
  • Inspect trace loading, ringing and powered-off devices clamping shared lines.

SPI data is shifted or corrupted

  • Verify mode, bit order, word length and CS duration.
  • Ensure DMA does not deassert CS before the final clock edge.
  • Reduce clock rate and inspect edges with an oscilloscope when decoding alone is misleading.

I²C is stuck low

  • Determine whether a slave is stretching SCL or holding SDA after an interrupted transfer.
  • Check shorts, pull-up values and voltage compatibility.
  • Apply the controller-and-device-specific bus recovery procedure.

RS-485 shows collisions or echoes

  • Check driver-enable timing so only one transmitter is active.
  • Verify end termination, biasing, polarity and a single defined cable topology.
  • Confirm that responses are sent only by the addressed node.

Design checklist

  • Identify the actual bus and its electrical voltage levels.
  • Draw shared versus dedicated signals and calculate CS or address resources.
  • Confirm selection, address uniqueness and reset-state behavior.
  • Record per-device timing, mode, clock, pull-up and termination requirements.
  • Plan error detection, timeouts, retries and recovery for stuck or powered-off devices.
  • Use a logic analyzer for protocol sequencing and an oscilloscope for signal integrity.

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