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Intel’s Knights Landing was the next generation of Xeon Phi, designed for high-performance computing (HPC) with either a socketed host-CPU configuration or a PCIe coprocessor. Intel disclosed the architecture in 2013 and introduced the Xeon Phi processor at ISC High Performance in June 2016. The “72-core” description fits specific models, including the Xeon Phi 7290 and 7290F—not every processor in the family.

What was Intel Knights Landing?

Knights Landing was Intel’s second-generation Many Integrated Core (MIC) architecture and the successor generation of its Xeon Phi products. Intel positioned it for highly parallel workloads such as scientific and engineering computing. Its design combined many CPU cores, wide-vector processing, and high-bandwidth on-package memory.

The name refers to an architecture and product generation, not one processor with a single fixed specification. Xeon Phi models built on Knights Landing came with different core counts and configurations.

Was Knights Landing a CPU or a coprocessor?

Intel’s original plan included two ways to deploy Knights Landing. The distinction was whether the chip served as the system’s host processor or accelerated work alongside a separate host.

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Configuration How it worked Platform role
Host processor Booted and ran applications natively; Intel said this avoided moving data to a separate accelerator over PCIe. Installed as the system’s CPU in a motherboard socket.
PCIe coprocessor Accelerated parallel work dispatched from a separate Xeon host, using the PCIe connection between host and accelerator. Added to a host system as a PCIe device.

In its June 17, 2013 announcement, Intel said: “When used as a CPU, ‘Knights Landing’ will also remove programming complexities of data transfer over PCIe, common in accelerators today.” That was Intel’s stated rationale for the host-processor option, not a guarantee of faster performance for every program.

Intel’s 2015 workshop material also described socketed, fabric-integrated, and PCIe-card concepts. These are deployment and platform-integration distinctions; the key choice for an application team was whether Knights Landing was the host CPU or a coprocessor.

How did Knights Landing’s architecture work?

Many-core CPU and vector processing

Intel’s 2015 workshop presentation described a self-booting processor with up to 72 cores, four hardware threads per core, two AVX-512 vector units per core, and a two-dimensional on-die mesh connecting components. The many-core design and vector units were aimed at processing large amounts of parallel work.

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On-package MCDRAM

Knights Landing integrated high-bandwidth MCDRAM memory on the processor package. Intel said the goal was to increase memory bandwidth for HPC applications and ease bandwidth bottlenecks. In its 2015 presentation, Intel specified more than 400 GB/s of MCDRAM bandwidth; this is a vendor figure, not a promise that all workloads would realize that rate or run faster.

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Intel’s peak compute figures

Intel’s 2015 workshop presentation cited more than 3 TFLOP/s of peak double-precision performance per package. This is an architectural peak from Intel, rather than an independent benchmark or a measure of performance for a particular application.

Which Xeon Phi models had 72 cores?

Intel ARK lists the Xeon Phi 7290 with 72 cores. Its listed specifications include 16 GB of memory, a 1.50 GHz base frequency, a maximum frequency of 1.70 GHz, 36 MB of L2 cache, and a 245 W thermal design power (TDP). ARK also lists the 72-core Xeon Phi 7290F with 16 GB of memory and a 260 W TDP.

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The core count was not uniform across the Knights Landing family. For example, Intel ARK lists the Xeon Phi 7210 at 64 cores. The headline’s 72-core count therefore describes particular models such as the 7290 and 7290F, not every Knights Landing processor.

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When did Knights Landing come out?

The announcement, host-CPU description, product introduction, and listed launch quarter refer to different milestones:

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Date Milestone
June 17, 2013 Intel disclosed Knights Landing at ISC’13, outlining plans for both PCIe coprocessor and host-CPU forms.
November 19, 2013 Intel described the host-CPU version as fitting standard racks and running applications natively rather than requiring offload.
June 20, 2016 Intel’s press kit dates the first introduction of the Xeon Phi processor (Knights Landing) to ISC High Performance in Germany.
Q4 2016 Intel ARK lists this as the launch quarter for the 7290 and 7290F.

What to check before buying legacy Knights Landing hardware

Intel’s historical product specifications establish what it announced and listed, but they do not establish current retail availability, used-market pricing, or compatibility with a particular server. Before evaluating a legacy system, verify the exact processor SKU, server-board support, cooling requirements, firmware, and memory arrangement with the system vendor or platform documentation.

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