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Intel’s Agilex update at Hot Chips 32 centered on a 10nm FPGA family that pairs programmable fabric with heterogeneous chiplets, rather than relying on a single monolithic die. Intel positioned Agilex for embedded, networking, and data-center workloads, highlighting second-generation HyperFlex, CXL and PCIe Gen 5 connectivity, advanced memory support, and DSP blocks for lower-precision AI and signal processing.
What Intel scheduled for Hot Chips 32
Intel’s media alert listed “Agilex Generation of Intel FPGAs” for Tuesday, August 18, 2020, from 8:30 to 10:00 a.m. Pacific. Ilya Ganusov and Mahesh A. Iyer were named as presenters. Intel said the session would provide an in-depth technical disclosure and reveal details about engineering-sample volume production. The Hot Chips 32 archive placed the talk in its FPGAs and Reconfigurable Architectures session, alongside a presentation on Xilinx Versal Premium.
That describes the announced scope of the session; it does not, by itself, establish the timing or volume of later commercial availability.
What Agilex changed architecturally
FPGA fabric with heterogeneous chiplets
Agilex combines FPGA fabric with chiplets in a system-in-package. Intel described possible chiplets for memory, transceivers, processor interfaces, data converters, and custom compute. The approach lets different functions use suitable process technologies and allows Intel to assemble targeted device mixes around a programmable core. Its central architectural distinction from a conventional single-die design is therefore packaging flexibility, not simply a faster FPGA fabric.
#1 Best Overall
- FPGA Evaluation Platform: DE25-Standard Development Kit designed for evaluation of Intel Agilex 5E FPGA (A5ED013BB32AE4SR1) for advanced programmable logic applications
- Development and Education Focus: Comprehensive development board from Terasic's DE Series, ideal for learning, prototyping, and testing FPGA-based designs and SoC implementations
- Rich Connectivity Options: Features multiple USB ports, Ethernet, audio jacks (pink, blue, green), GPIO expansion headers, and various interfaces for versatile project development
- Interactive Components: Equipped with onboard buttons, switches, LED displays, and indicators enabling hands-on experimentation and debugging of digital logic designs
- Professional Grade Hardware: Robust construction weighing 2.425 pounds with high-quality PCB design, providing a stable platform for complex FPGA development projects
Second-generation HyperFlex
The fabric uses Intel’s second-generation HyperFlex architecture. Hyper-Registers are distributed through routing and at functional-block inputs, giving designers additional points for retiming logic and improving timing. Intel also described a high-speed bypass intended to benefit both HyperFlex-optimized designs and conventional designs. In practical terms, the architecture aims to help close timing in complex datapaths; the available claims do not mean that every design will achieve the same frequency or power improvement.
Connectivity, memory, and acceleration capabilities
Intel’s 2019 launch material listed Compute Express Link (CXL), PCI Express Gen 5, transceivers rated up to 112 Gbps, and support for DDR5, high-bandwidth memory (HBM), and Intel Optane DC persistent memory. Intel’s technical white paper describes portfolio variants with transceivers up to 116 Gbps and Ethernet blocks up to 400 Gb. The 112- and 116-Gbps figures come from different Intel materials and should be read as stated capabilities across the family, not as one guaranteed rate for every Agilex device.
Rank #2
- FPGA Development Platform: Atum A5 Agilex 5 E-Series SoC FPGA development board featuring the A5ED065B chip for advanced programmable logic applications
- Complete Kit: Includes development board, USB and power cables, power supply adapter, and accessories for immediate setup and evaluation
- Connectivity Options: Equipped with FMC+ and MIPI (CSI/CSI-2/DSI/DSI-2) interconnect systems for flexible peripheral and camera interface integration
- Compact Design: Board measures 6.3 inches x 6.1 inches (160 mm x 155 mm), providing a space-efficient platform for FPGA and MCU/MPU SoC development
- USB Interface: Features USB connectivity for easy programming, debugging, and communication with host computer systems
CXL and PCIe Gen 5 address high-bandwidth attachment to processors and other system components, while the memory options support different capacity, bandwidth, and persistence needs. High-speed serial links and Ethernet blocks suit network-facing systems. Actual interface availability depends on the selected device variant and system design; these family-level descriptions do not imply that every option appears together in one part.
Agilex DSP blocks support FP16 and bfloat16 (BFLOAT16), formats relevant to AI inference and signal-processing workloads. Intel’s 2019 release claimed up to 40 TFLOPs of FP16 DSP performance, derived from the number of DSP blocks and their maximum clock frequency. Its technical white paper gives up to 38 TFLOPs for FP16/BF16 or 19 TFLOPs for FP32 for a specified configuration. Those are Intel architecture or configuration-based figures, not measured application throughput, and the differing precision modes and stated basis matter when comparing them.
Rank #3
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
How Intel’s Agilex performance claims compare with Stratix 10
| Intel source | Claim relative to Stratix 10 | Qualification |
|---|---|---|
| Intel Corporation, 2019 launch material | Up to 40% higher performance, or up to 40% lower total power | Based on an example design suite and Intel internal analysis; tests were conducted in February 2019. |
| Intel Corporation, technical white paper | 50% higher performance on a geometric-mean basis, or up to 40% lower power | Intel’s white-paper comparison; the cited summary does not provide matching test details sufficient to equate it directly with the launch-material figure. |
These are vendor comparisons, not universal guarantees for every design. The launch material and white paper describe different performance figures, and the stated evidence does not establish that they use identical design sets or measurement methods. A buyer evaluating a particular workload should compare its own implementation, including toolchain, timing closure, power conditions, and device selection, rather than treating either percentage as a blanket product advantage.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the update means for FPGA selection
Agilex’s feature set points to systems that need a mix of programmable acceleration and high-speed I/O: data-center adapters, network equipment, and embedded platforms are consistent with Intel’s stated target markets. The architecture also offers a way to combine fabric with selected package-level functions, while the DSP precision support is relevant where FP16 or BF16 arithmetic fits an inference or signal-processing workload.
Rank #4
- Altera Cyclone IV FPGA includes 6,000 Logic Elements with two clock multipliers. The Cyclone IV FPGA is the perfect balance of inexpensive cost versus plentiful logic cells, 20KBytes of SRAM, and General Purpose Input/Output pins. This is a great board to learn how to program FPGA's.
- Built in programmer cable allows configuring the FPGA with a single USB-C cable. The DPL can be powered from the USB cable or from the Barrel Connector. A separate JTAG header can also be used to program the FPGA using a compatible USB Blaster cable.
- 6x6 LED Array allows character and animations to be displayed at ultra fast speed. LED blocks can be individually turned on/off to allow LED signals to be used as I/O's
- 70 Inputs/Outputs originating at the FPGA are available at Stackable Headers organized around the edge of the board. The user can configure these I/O's using the FPGA project code.
- The DPL contains two oscillators, 66MHz and 100MHz. The 66MHz oscillator is used to provide clocking for the EPT ActiveHost USB communications core. The 100MHz oscillator can be used by the user clocked up using one of the onboard Clock-DLL modules.
For a practical comparison with Stratix 10 or another FPGA family, evaluate these factors against the actual design:
Quick Recap
Best Value
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
- Fabric performance and power: Compare implementation results for the same workload and constraints, not only family-level percentages.
- Package and chiplet options: Check which transceivers, memory, processor interfaces, converters, or custom compute functions are available in the specific device.
- External I/O: Match required transceiver and Ethernet rates, and confirm the needed protocol blocks and board-level support.
- Memory and interconnect: Determine whether the design needs DDR5, HBM, persistent memory, CXL, PCIe Gen 5, or some combination.
- DSP precision: Verify that the required arithmetic mode and real application throughput meet the workload’s needs.
- Toolchain and workload fit: Evaluate software support and implementation effort alongside whether the target is edge, network, or data-center acceleration.
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