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What XML can specify in an ASIC or SoC project
IP-XACT describes metadata about intellectual-property designs and flows, including how IP interfaces are interconnected. Its document model can capture component definitions, interfaces, parameters, ports, registers, implementation views, and references to implementation files. It also represents designs and design configurations for composing components into a hierarchy.
That makes IP-XACT useful as a shared integration description for IP providers, SoC architects, and EDA tools. It can record what a block exposes and how blocks fit together without replacing the implementation itself: RTL, SystemC, or other referenced files still carry the implementation details appropriate to their format.
For a practical project, decide which information is authoritative in XML and which remains authoritative in source code or another system. In particular, assign ownership for component names, interfaces, parameters, clocks and resets, address maps, and implementation views. Without explicit ownership, XML and RTL can drift apart even when both are individually valid.
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IP-XACT and CMSIS-SVD: which should you use?
These formats overlap around register descriptions, but they serve different jobs. CMSIS-SVD is an XML format influenced by IP-XACT and scoped to a device’s software-facing view. It describes one device’s processor, peripherals, registers, fields, and optional enumerated values; it is not a general model for assembling a hierarchical SoC.
| Decision area | IP-XACT / IEEE 1685 | CMSIS-SVD |
|---|---|---|
| Scope | Reusable IP packaging, interfaces, implementation views, designs, catalogs, generators, and interconnect metadata. | One device’s programmer-visible processor, peripherals, registers, fields, and optional enumerated values. |
| Typical audience | IP providers, SoC architects, integration teams, and EDA tools. | Firmware developers and device-description tooling. |
| Best fit | A canonical integration model for reusable IP and SoC construction. | A software-facing register map and device description. |
| Compatibility concern | IEEE 1685 release, namespace and schema version, vendor extensions, and support in consuming tools. | SVD version and support in the CMSIS or device tools that consume the file. |
| Automation role | Metadata access, component and design views, generator interfaces, and integration workflows. | Consumption of peripheral and register descriptions by software-facing tools; broader SoC assembly is outside its intended scope. |
Use both when the project needs a broad hardware-integration model and a software-ready device description. Define how the two representations stay synchronized; do not assume one automatically replaces the other.
Build an IP-XACT specification in a controlled sequence
IP-XACT has multiple document types rather than one all-purpose XML file. The IEEE 1685-2022 User Guide lists component, design, design-configuration, bus-definition, abstraction-definition, type-definition, abstractor, generator-chain, and catalog documents. Choose the documents your flow needs and keep their references consistent.
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Set vocabulary and ownership
Agree on naming, units, interface conventions, parameter ownership, clock and reset descriptions, address-map ownership, and which view defines each implementation artifact. Establish how changes in RTL or integration data are reflected in the other.
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Choose and pin the IP-XACT release
Select the IEEE 1685 generation and namespace/schema policy expected by your tools. Record that choice in the project and in validation automation. Accellera publishes material for multiple generations, so “IP-XACT XML” by itself is not a sufficiently precise compatibility target.
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Describe reusable components
Create component documents for blocks and capture their relevant ports, bus interfaces, parameters, registers, views, and references to implementation files such as Verilog, VHDL, or SystemC. Keep the component description aligned with the actual block interface and intended reuse boundary.
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Compose subsystems and the SoC
Use design and design-configuration documents to describe hierarchy and integration. Depending on the project and tool support, the model can represent logical interconnect, memory maps, and physical interconnect views. Keep this system-level composition distinct from the reusable component definitions it instantiates.
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Validate structure, then check meaning
Validate each document against the XSD for the selected release. Follow that with semantic consistency checks for project rules that XML Schema structure alone cannot establish—for example, whether references resolve and whether independently described integration information agrees. Use the semantic rules and tool support available for the selected release.
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Connect the model to generators and tools
Use supported generators or adapters to produce or synchronize structural HDL, integration metadata, register headers, documentation, or verification collateral. Generator commands and capabilities are tool-specific: IEEE 1685 supplies a metadata model and access approach, not a universal command that generates a complete design.
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Maintain the firmware-facing description
For software consumers, emit or maintain CMSIS-SVD alongside the broader IP-XACT model. Include the device, processor, peripherals, registers, fields, and enumerated values that the firmware tooling needs, and establish how changes to those details are carried across representations.
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Run the normal hardware verification and signoff flow
Continue with RTL checks, simulation or formal verification, clock-domain-crossing and reset analysis, timing and power analysis, DFT, physical design, and implementation signoff as required by the project. A schema-valid XML file says nothing by itself about functional correctness or whether a chip meets implementation constraints.
What XSD validation does—and does not—tell you
An XSD check tests whether an XML document conforms to the selected schema’s structure and declared constraints. Accellera publishes XSD files intended for validating documents conforming to IEEE 1685-2014. That is useful for catching malformed documents and structural mismatches, but it should not be confused with a full check of project-specific meaning.
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- Structural validation: confirms conformance to the schema version being used.
- Semantic consistency: checks relationships and project rules that the XSD alone does not express.
- Hardware correctness: requires the ordinary verification and implementation flows; XML validity cannot establish it.
Accellera’s IP-XACT working-group material reports approval in June 2023 of supplemental material for IEEE 1685-2022, including recommended vendor extensions, schemas, semantic consistency rules, and a portable generator interface. The IEEE 1685-2022 User Guide was listed on Accellera’s download page in September 2023. These release details make it especially important to identify the exact schema and tool support used by a project rather than assuming every IP-XACT tool accepts every generation or extension.
Plan for interoperability and tool differences
The standard’s portability goal does not mean every tool implements every feature identically. Before adopting a model across teams or vendors, agree on the IEEE 1685 release, namespace policy, allowed vendor extensions, and the subset of document types and generators the flow will use. Confirm how a tool reads, writes, and preserves those details.
Accellera describes an API for tool access to metadata and a portable generator interface intended to improve portability of design data, methodologies, and environment implementations. In practice, automation still depends on the adapters and generators available in the chosen toolchain. Treat generated artifacts as outputs that need defined ownership and verification, not as guaranteed consequences of merely having an XML specification.
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