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Yes. A CD4069UB can form an RC relaxation oscillator in LTspice, but the most reliable workflow is to verify the circuit first with an ideal behavioral inverter, then substitute Texas Instruments’ CD4069UB PSpice subcircuit. The ideal model starts quickly and makes the timing equation clear; the vendor model reveals threshold, loading, delay and startup effects that can move the real frequency away from the simple calculation.
How the CD4069 RC oscillator works
One unbuffered CMOS inverter drives a resistor whose other end is the inverter input. A capacitor connects that input node to ground. The output changes state when the capacitor voltage crosses the inverter’s switching threshold. The resistor then charges or discharges the capacitor in the opposite direction, repeating the cycle. A second inverter can buffer the timing signal so an external load does not significantly disturb the RC network.
Use the exact device designation when possible. TI’s CD4069UB datasheet describes a six-section, unbuffered CMOS inverter with a recommended 3–18 V supply range, pin assignments and a typical RC oscillator. “CD4069” is also used generically for parts from other manufacturers, whose thresholds and model pin orders may differ.
Because the CD4069UB is unbuffered, do not treat it like a CD40106-style Schmitt trigger. Its switching behavior is more sensitive to supply voltage, temperature, loading, leakage and layout, and the datasheet does not make it a precision RC-frequency reference.
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- Wide supply voltage range: 3.0V to 15V
- High noise immunity: 0.45 VDD typ
- Low power TTL compatibility
- The product has been strictly selected and has stable performance
- NOTE:Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Fastest LTspice demonstration: an ideal inverter
This self-contained netlist runs without a vendor library and is useful for checking topology, startup and approximate timing.
* Ideal CD4069-style RC oscillator demonstration
.param VDD=5
.param Rtim=100k
.param Ctim=10n
V1 vdd 0 {VDD}
B_INV nsw 0 V=if(V(ntiming)>{VDD/2},0,{VDD})
B_BUF vout 0 V=if(V(nsw)>{VDD/2},{VDD},0)
R1 nsw ntiming {Rtim}
C1 ntiming 0 {Ctim}
.ic V(ntiming)=0
.tran 0 10m 0 1u startup
.meas tran Tper TRIG V(vout) VAL=2.5 RISE=10 + TARG V(vout) VAL=2.5 RISE=11
.meas tran Freq PARAM 1/Tper
.endIn a schematic, place a supply, resistor, capacitor, two behavioral voltage sources and ground, then add the .ic and .tran directives. Probe V(ntiming), V(nsw) and V(vout). The timing node is a charge-and-discharge waveform; the buffered node is square-like.
Transient settings that usually work
- For approximately 700 Hz, use
.tran 0 10m 0 1u startup. - For a slower oscillator, extend the stop time, for example
.tran 0 1 0 100u startup. - For a faster oscillator, reduce the maximum timestep, for example
.tran 0 1m 0 10n startup. - Keep the maximum timestep substantially shorter than one period so transitions and measurement crossings are resolved.
Starting frequency calculation
With an ideal inverter that switches symmetrically at half the supply, each half-cycle takes RC ln(2). Therefore:
Rank #2
- Pack of 10 Pcs; DIP-14 Package
- Logic Function: Hex Inverter (6 Channels)
- Voltage Range: 3V to 18V
- high input impedance (10pA typ)
T ≈ 2RC ln(2)
f ≈ 1/(2RC ln(2))
For 100 kΩ and 10 nF, the ideal estimate is T ≈ 1.386 ms and f ≈ 721 Hz. This is a derived result for the assumed behavioral model, not a CD4069UB frequency specification.
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| Target frequency | Capacitor | Approximate resistor |
|---|---|---|
| 10 Hz | 1 µF | 72.1 kΩ |
| 100 Hz | 100 nF | 72.1 kΩ |
| 1 kHz | 10 nF | 72.1 kΩ |
| 10 kHz | 1 nF | 7.21 kΩ |
| 100 kHz | 100 pF | 7.21 kΩ |
For a real inverter, let the rising and falling switching thresholds be normalized to supply as αH and αL. A useful model-analysis expression is:
tcharge = −RC ln(1 − αH + αL)
tdischarge = −RC ln(αL/αH)
Rank #3
- CD4069UBM SOP-14 CD4069 CD4069BM Hex Unbuffered Inverter IC, SOIC-14, CMOS Logic Gate (CD4069U)
- Contains six independent CMOS unbuffered inverters (NOT gates), providing the basic inverting logic function.
- The "unbuffered" design offers higher gain and faster transition times under specific conditions, but less output drive.
- Available in the SOIC-14 package format, a common and versatile footprint for logic ICs on surface-mount PCBs.
- Applications include crystal oscillators, Schmidt triggers (with external components), analog amplifiers, pulse shapers, and simple logic inversion.
The sum explains frequency error when thresholds are not exactly VDD/2. Do not use these equations as guaranteed CD4069UB limits without threshold data for the exact supply, temperature, load and device.
Importing the CD4069UB vendor model
TI provides a downloadable CD4069UB PSpice Model, Rev. A from its CD4069UB product page. A PSpice model is not automatically an LTspice model; syntax, dependencies and symbol pin order must be verified.
- Download and extract the model into the same project folder as your schematic.
- Open the model text and find the
.SUBCKTdeclaration. Record its subcircuit name, pin order, supply pins and whether it models one inverter or the complete package. - Use LTspice’s official subcircuit workflow: place the file in a user or project directory, open it, right-click the
.SUBCKTline, choose Create Symbol, and save the symbol beside the model. The procedure is documented by Analog Devices at Create a Symbol from ADI subcircuit or library file. - In the schematic, press P or choose Place Component, select Refresh, then User Files, and place the generated symbol.
- If LTspice does not find the library automatically, add a project-local directive such as
.include CD4069UB.lib, using the actual filename and path. - Run a one-inverter test before rebuilding the oscillator. Confirm that the symbol’s pins match the
.SUBCKTdeclaration exactly.
Keep the symbol, library and schematic together. LTspice’s library and symbol search paths behave differently, and moving only one file commonly produces “model not found” errors. The LTspice transient controls, including starting external supplies at 0 V and skipping the initial operating-point solution, are described in the LTspice startup guide.
Rank #4
- Standardized symmetrical output characteristics
- Medium speed operation: tPHL, tPLH = 30 ns at 10 V (Typical)
- 100% Tested for quiescent current at 20 V, Meets all requirements of JEDEC tentative standard No. 13B, Standard Specifications for Description of B Series CMOS Devices
- Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
- Example Applications: Logic inversion, Pulse shaping, Oscillators, High-input-impedance amplifiers
CD4069UB pinout checks
For the TI package, pin 14 is VDD and pin 7 is VSS. The six inverter pairs are:
| Section | Input | Output |
|---|---|---|
| A/G | 1 | 2 |
| B/H | 3 | 4 |
| C/I | 5 | 6 |
| D/J | 9 | 8 |
| E/K | 11 | 10 |
| F/L | 13 | 12 |
- Do not reverse an input and output.
- Connect both supply pins.
- Do not assume the six sections are internally connected.
- Tie every unused CMOS input to ground or VDD; never leave it floating. Keep its output unconnected unless it has a defined purpose.
- Check that the timing capacitor is on the inverter input side of the feedback resistor.
Why the real simulation differs from 721 Hz
| Effect | What changes |
|---|---|
| Threshold voltage | Unequal or supply-dependent thresholds alter charge and discharge times. |
| Output resistance | The inverter’s finite drive resistance becomes important with low timing resistance. |
| Leakage and probe loading | Very high timing resistance makes small currents and board contamination significant. |
| Capacitor tolerance and parasitics | Actual capacitance may differ from its nominal value, especially with small ceramic parts. |
| Load capacitance | Directly loading the timing inverter rounds edges and can shift timing; use a spare inverter as a buffer. |
| Supply and temperature | Frequency and logic swing can change across the CD4069UB’s 3–18 V operating range and temperature range. |
TI specifies low input current, including 1 µA maximum at 18 V over the full temperature range and 100 nA typical at 18 V and 25 °C. Those figures do not make arbitrarily large timing resistors accurate: resistor value, capacitor leakage, PCB leakage and the required frequency tolerance still determine the error.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Troubleshooting an oscillator that fails
No oscillation
- Add
.ic V(ntiming)=0or a small offset such as.ic V(ntiming)=1m. - Run with
startupso supplies begin at zero instead of relying only on the operating-point solution. - Check inverter polarity, feedback direction, capacitor wiring and supply pins.
- Test the inverter alone before inserting it into the feedback loop.
Convergence failure
- Reduce the maximum timestep.
- Use
startupand a defined capacitor initial voltage. - Add small realistic parasitic resistances.
- Remove unnecessary ideal sources.
- Use the behavioral model to determine whether the topology works, then inspect unsupported PSpice syntax in the vendor model.
Waveform stuck at one rail
Verify that the timing node is not shorted, the resistor connects from output to input, the model pin order is correct and the behavioral threshold expression uses the intended supply voltage.
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Measure steady-state cycles rather than the first transition. The example .meas statement measures the interval between the tenth and eleventh rising crossings. Choose a measurement level inside the logic swing; a fixed 2.5 V crossing is appropriate only for a 5 V example. A real CD4069UB threshold need not equal half the supply.
Vendor model will not import
- Confirm every dependent file is present.
- Match the symbol value to the exact
.SUBCKTname. - Re-create the symbol from the correct subcircuit line.
- Use a local
.includedirective. - If LTspice rejects PSpice syntax, retain the ideal model as an explicitly labeled approximation rather than silently changing the circuit.
Choosing a different oscillator device
Use a CD4069UB when an unbuffered CMOS inverter is specifically required and approximate RC timing is acceptable. A Schmitt-trigger inverter is generally easier for a robust RC oscillator because its hysteresis improves noise immunity and startup behavior. A 555-style timer suits a conventional adjustable relaxation oscillator. Choose a crystal oscillator, dedicated clock generator or microcontroller timer when frequency accuracy, calibration, temperature stability or programmability matters.
Neither the ideal behavioral circuit nor a vendor subcircuit proves that hardware will meet a tight tolerance. Validate the chosen resistor, capacitor, supply, load, temperature range and PCB implementation on the physical circuit.
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