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Reduce capacitor stress by managing four variables together: RMS ripple current, electrical margin, heat flow, and verification under the server’s real duty cycle. The practical sequence is to measure or model ripple current, select capacitors with adequate voltage and temperature derating, lower ESR and thermal resistance, spread current across a correctly designed bank, and validate temperatures and lifetime at sustained load. A short peak-load test is not enough for an AI-server power supply that may operate near maximum power continuously.
Why high-density server PSUs stress capacitors so severely
Capacitors in a conventional desktop supply may have comparatively generous spacing, airflow and thermal margin. A high-density server PSU removes much of that margin. AI accelerators and other dense compute systems raise input current, switching frequency, heat generation and component packing at the same time. The capacitor can therefore see higher electrical ripple while sitting in a hotter, less ventilated location.
AIC tech describes the consequence plainly: “In AI server applications, capacitors have become so critical that it is no exaggeration to say that ‘capacitor selection is power supply design.’” The statement is particularly relevant to bulk capacitors on the rectified bus and to input and output capacitors in high-frequency converter stages.
Stress is not one failure mechanism. It is a combination of:
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- Ripple-current heating: alternating current dissipates power in ESR (equivalent series resistance).
- Voltage stress: bus voltage, switching overshoot, surge and inrush must remain below the capacitor’s maximum rating.
- Thermal stress: nearby FETs, rectifiers, magnetics and restricted airflow raise the capacitor’s internal temperature.
- Aging feedback: capacitance generally declines and ESR rises with age, increasing ripple voltage and self-heating.
- Mechanical and environmental stress: vibration, vent obstruction, contamination and poor service access can turn an electrically adequate part into a field failure.
The design objective is not simply “use a larger capacitor.” It is to keep electrical and thermal stress below the limits for the entire intended life, including worst-case line, load, airflow and end-of-life conditions.
Start with ripple-current heating
Use the thermal relationship
For a first-order estimate, TDK gives the capacitor core-temperature rise as:
ΔT = i² × ESR × Rth
Here, i is RMS ripple current, ESR is equivalent series resistance and Rth is the thermal resistance from the capacitor’s heat-generating core to its surroundings. The equation identifies three direct levers:
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- Use a lower-ESR capacitor appropriate for the switching frequency and temperature.
- Reduce thermal resistance with spacing, airflow and a better conduction or heat-spreading path.
Because current is squared, a modest reduction in RMS ripple can have a disproportionately large effect on internal heating. Calculate the actual waveform rather than using only the converter’s average current. Pulsating input current, discontinuous conduction, interleaving and high-frequency switching can produce RMS values that are much higher than the DC current visible on a system power meter.
Share current across a parallel bank
Putting capacitors in parallel divides ripple current when their impedances and connections are reasonably matched. Lower current in each part reduces the i² heating term and can increase the bank’s total ripple-current capability. AIC identifies current distribution among multiple capacitors as a way to reduce both thermal and electrical stress.
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Parallel operation is not automatically balanced. Use equal or deliberately characterized parts, symmetrical copper paths and low-inductance connections. Check the impedance of each branch, including busbar and trace resistance, because one capacitor can carry substantially more current than another. Confirm that the bank’s combined capacitance, ESR and ESL do not create a resonance or alter converter-control behavior. Also check inrush current and the discharge path: adding capacitance can increase both.
Choose a capacitor technology for the waveform and environment
Technology selection should follow the electrical and thermal conditions, not a blanket preference for one chemistry. The following comparison describes the categories relevant to switching server supplies; the final part must still meet the manufacturer’s ratings at the intended frequency and temperature.
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| Technology | Useful characteristics | Checks before substitution |
|---|---|---|
| Aluminum electrolytic | High capacitance and practical bulk-energy storage; widely used for rectified-bus hold-up. | Voltage derating, ripple-current rating, lifetime at hotspot temperature, ESR rise with age, polarity, vent clearance and allowable ripple frequency. |
| Conductive-polymer aluminum electrolytic | Typically lower ESR and strong high-frequency ripple performance; a plausible low-loss alternative or redesign category. | Control-loop stability, capacitance and voltage range, ripple-current rating, lifetime definition, leakage, polarity, package dimensions, inrush and mechanical fit. |
| MLCC | Very low ESL and effective high-frequency decoupling in a small volume. | DC-bias capacitance loss, voltage rating, cracking and board-flex risk, acoustic or piezoelectric effects where relevant, and whether the remaining capacitance is adequate at operating bias. |
Analog Devices lists low-ESR polymer capacitors and MLCCs as common high-performance choices for switching-supply input filtering, provided their voltage derating and RMS ripple-current capability are sufficient. Panasonic notes that output ripple depends on inductor ripple current, capacitance, ESR and ESL; when larger aluminum electrolytics are used, low ESR is necessary to limit ripple voltage.
Do not optimize ESR in isolation
A single very-low-ESR part can create a new problem. Converter compensation may have been designed around a particular capacitor impedance. A large ESR reduction can change loop zeros and phase margin, while the combination of low ESR and wiring inductance can produce ringing. Recheck control-loop stability, transient response, inrush limiting, damping and conducted-emissions behavior after changing technology or bank size.
Apply voltage derating to every operating condition
The capacitor’s nominal voltage rating must exceed the highest voltage that can occur at its terminals, with design margin. Infineon’s 8 kW server-PSU application note explicitly requires bulk voltage to remain below the electrolytic capacitor’s maximum rating and capacitor current stress to remain within its ratings. Analog Devices likewise recommends sufficient voltage derating for switching-supply input capacitors.
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Check more than nominal high-line operation:
- Steady-state high line: include rectifier tolerance, regulation error and measurement uncertainty.
- Load steps: capture overshoot when load falls abruptly and the control loop unloads stored energy.
- Line events: test surge, brownout recovery and line dropout. A PFC stage can produce a different bus trajectory during each event.
- Inrush: include pre-charge, relay or active-inrush timing and a discharged capacitor at power-up.
- Control faults: consider a gate-drive or feedback fault that allows an abnormal duty cycle or bus rise.
Use the measured terminal waveform, not only a controller set point, when selecting the rating. A capacitor that survives the average bus voltage can still be overstressed by repetitive switching overshoot.
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Separate capacitors from heat sources
Place capacitors away from switching FETs, rectifiers, magnetics and hot heatsink exhaust whenever the mechanical design permits. AIC reports that dense mounting and nearby heat sources can raise capacitor operating temperature by 10–20 °C relative to the original design assumption. Treat that range as an engineering observation for dense layouts, not as a universal correction factor.
Model the complete thermal path: core to case, case to sleeve or clamp, mounting interface, local air and finally the system exhaust. The case temperature can look acceptable while the internal winding or foil is hotter. TDK identifies both ESR and thermal resistance as primary parameters to optimize when limiting core-temperature rise.
Protect the airflow path
- Keep inlet and outlet paths open around the capacitor bank; do not place cable bundles directly in the local flow channel.
- Avoid recirculation zones behind heatsinks or at the fan’s dead spot.
- Use spacing that allows air to reach the body and prevents one hot part from preheating the next.
- Where appropriate, provide conduction to a chassis or heat spreader, while respecting the capacitor manufacturer’s mounting and insulation limits.
- Check the degraded-airflow case, such as a clogged filter, failed fan or reduced fan speed, rather than validating only a clean, full-speed system.
Surface temperature measurements are useful for screening but cannot by themselves establish core temperature. Use the manufacturer’s thermal data to estimate the internal temperature from measured case and nearby-air temperatures.
Size the bank within density and hold-up constraints
High-density supplies force tradeoffs among bulk capacitance, hold-up energy, efficiency, switching frequency, thermal margin and volume. Infineon’s 3.3 kW high-density server-PSU reference design cites a 97.5% peak efficiency at 230 VAC, a minimum power density of 32.15 W/in³ (1.96 W/cm³), and 20 ms of hold-up time at full load. These are reference-design figures from Infineon in 2025, not universal requirements for every server.
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| System constraint | Published reference figure | Design implication |
|---|---|---|
| Peak efficiency | 97.5% at 230 VAC | Less loss is available to heat the enclosure, but the remaining loss is concentrated in a smaller volume. |
| Power density | 32.15 W/in³ (1.96 W/cm³) minimum | Capacitor spacing and airflow must be designed alongside magnetic and semiconductor placement. |
| Hold-up | 20 ms at full load | Bulk energy must remain sufficient at the minimum allowed bus voltage and at end of life. |
Stored energy is related to capacitance and voltage by E = ½ C(Vhigh2 − Vlow2). Use the actual permissible bus-voltage window and the converter’s full-load power when determining whether the bank can sustain the required hold-up interval. Include capacitor tolerance, aging-related capacitance loss, ESR-induced voltage drop and control margins.
Infineon’s 8 kW design describes reducing bulk capacitance as a possible density strategy, but only when hold-up, PFC operation, voltage and current-stress criteria continue to be met. Removing capacitance to save volume is therefore a system redesign, not a drop-in component change.
A step-by-step design workflow
- Define the operating envelope. Record input-voltage range, frequency, load range, ambient temperature, altitude if relevant, fan-speed limits, expected duty cycle and required hold-up time. Include sustained near-peak AI-server loading rather than treating peak power as a brief event.
- Map every capacitor location. Identify PFC bulk parts, converter input and output capacitors, high-frequency decouplers and any snubbers. For each location, document DC voltage, switching frequency, waveform shape, polarity and available cooling.
- Obtain RMS ripple current. Derive it from a validated converter model or measure it with suitable current instrumentation. Evaluate the worst combination of line, load, switching frequency, temperature and control mode. Compare the result with the datasheet ripple-current rating at the same frequency and temperature.
- Select voltage and temperature margins. Apply derating to the highest measured terminal voltage, including transients. Calculate the hot-spot temperature, not merely room ambient, and verify the manufacturer’s endurance or lifetime rating at that temperature.
- Choose technology and bank topology. Compare aluminum electrolytic, conductive-polymer aluminum electrolytic and MLCC options against ESR, ESL, capacitance under bias, ripple current, lifetime, size and failure mode. If using parallel parts, design symmetrical current paths and verify balancing.
- Check converter interaction. Recalculate control-loop compensation, resonances, damping, inrush, discharge time and transient response after changing capacitance or ESR. Confirm that the replacement does not create an unstable or poorly damped input filter.
- Lay out the thermal path. Move capacitors away from heat sources, preserve airflow, provide approved conduction paths and leave vent clearance. Review the layout at the full mechanical assembly level, including cables, shields and fan ducts.
- Recalculate end-of-life behavior. Apply the manufacturer’s capacitance and ESR aging model. Verify that hold-up, ripple voltage, control stability and current sharing remain acceptable when the bank reaches its specified end-of-life limits.
- Validate hardware under representative duty. Test sustained load, line events, load steps, inrush and restricted-airflow corners. Record electrical waveforms and temperatures, then compare them with the design calculations.
How to validate a capacitor bank
A credible validation plan combines electrical measurements, thermal measurements and lifetime calculations. The following checklist covers the minimum evidence to collect:
- Capture terminal voltage. Measure capacitor voltage during startup, steady state, high-line operation, load steps, line dropout, surge and shutdown. Use probing that does not add a long ground lead or hide high-frequency overshoot.
- Measure RMS ripple current per part. Where possible, measure each parallel branch rather than only the total bank. Compare the measured waveform and RMS value with the datasheet rating at the actual operating frequency and temperature.
- Measure case and local-air temperatures. Place sensors on the capacitor body and in the nearby airflow. Use the manufacturer’s thermal impedance information to estimate core temperature; do not treat case temperature as a direct substitute.
- Run sustained representative load. Hold the supply at the continuous load expected in service. Include long-duration near-peak operation, because a brief load pulse may not reach thermal equilibrium.
- Test airflow corners. Repeat the test with fan degradation, blocked or dirty filters, reduced fan speed or the worst permitted rack orientation when those conditions are part of the product specification.
- Recalculate lifetime. Combine hot-spot temperature, ripple current, voltage, capacitance loss and ESR growth. Confirm that end-of-life values still satisfy hold-up and ripple limits.
- Inspect the assembly. Look for hot spots, blocked airflow, vibration, inadequate vent clearance, stressed leads or terminals and poor service access. Mechanical findings can explain thermal results that an electrical model misses.
Diagnose common failure patterns
| Observed symptom | Likely stress mechanism | Checks and corrective actions |
|---|---|---|
| Case temperature rises rapidly with load | Excess RMS ripple, high ESR or inadequate airflow. | Measure branch current, verify the datasheet rating at the real frequency, calculate i² × ESR × Rth, improve spacing or airflow, and consider a lower-loss technology. |
| One capacitor in a parallel bank runs hotter | Unequal impedance or asymmetrical copper paths. | Measure current in each branch, shorten or equalize connections, match parts and check for a damaged or aging capacitor increasing its own ESR. |
| Vent opening, bulging or leakage | Overvoltage, excessive core temperature, ripple beyond rating or end-of-life degradation. | Capture voltage transients, check ripple and thermal data, inspect inrush and line events, and replace the bank only after correcting the initiating stress. |
| Unexpected ringing or control instability after a capacitor change | ESR/ESL or capacitance changed the input filter or feedback-loop dynamics. | Recheck compensation, impedance plots, damping, layout inductance and transient response; do not assume a lower ESR part is electrically interchangeable. |
| Hold-up time fails late in life | Capacitance loss, increased ESR or an overly small initial bank. | Use aged capacitance and ESR in the energy calculation, verify the minimum bus-voltage threshold and increase energy storage or revise the hold-up requirement. |
Account for aging and lifetime feedback
Capacitor lifetime is governed by the temperature and electrical stress at the actual hotspot, not by the room-temperature label on the enclosure. As the capacitor ages, capacitance can decline and ESR can rise. The higher ESR increases ripple heating; the higher temperature accelerates aging, creating a feedback loop.
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Use the manufacturer’s endurance model and apply the conditions that match the installation:
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- Hot-spot temperature over the complete load and airflow profile.
- RMS ripple current at the relevant frequency, including harmonics where the datasheet requires them.
- Voltage bias and repetitive transients.
- Continuous operating hours and the expected fraction of time at near-peak load.
- Capacitance tolerance and the specified end-of-life ESR or capacitance limit.
For an AI-server power supply, assume that high utilization can persist for hours or days unless the deployment profile proves otherwise. A lifetime calculation based on short benchmark bursts can substantially understate thermal exposure.
Compare candidate capacitor banks before purchasing
Make the comparison at the bank level, not by looking at one headline specification. Record these fields for every candidate:
- Rated voltage and the applied steady-state and transient derating.
- RMS ripple-current rating at the actual frequency and operating temperature.
- ESR and impedance over frequency, including tolerance and aging information.
- Capacitance tolerance and DC-bias behavior where applicable.
- Endurance or lifetime at the calculated hotspot temperature.
- Physical diameter, height, terminal arrangement, spacing, vent clearance and airflow exposure.
- Polarity, inrush implications, discharge requirements and failure mode.
- Control-loop, resonance and EMI impact of the complete bank.
- Total bank cost, including the number of parts, balancing hardware and assembly changes.
The most defensible product category for a low-loss redesign is a conductive polymer aluminum electrolytic capacitor with low ESR. That phrase describes a category, not a universal replacement. Match voltage, capacitance, ripple-current rating, ESR, lifetime, polarity, dimensions and control-loop requirements before ordering any part. Exact availability and pricing vary by distributor and were not established here.
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- If ripple current is the dominant heat source, reduce RMS current first, then lower ESR and share current across a properly balanced bank.
- If voltage margin is narrow, correct the transient or control condition before selecting a higher-rated part; a higher rating does not remove the underlying overshoot.
- If the capacitor is cool at light load but overheats during sustained AI workloads, redesign for the continuous duty cycle and inspect airflow recirculation.
- If a polymer or MLCC substitution changes impedance substantially, repeat loop-stability, inrush and EMI validation.
- If measured surface temperature looks safe but lifetime calculations fail, treat the internal core estimate and manufacturer thermal model as the governing evidence.
- If reducing bulk capacitance is necessary for density, re-prove hold-up, PFC operation, voltage stress and current stress at end of life.
Capacitor stress falls only when the electrical waveform, component impedance, thermal path and validation method agree. Design the bank for the real server workload, then prove its voltage, ripple, temperature and lifetime margins with measurements that include the worst permitted operating and airflow conditions.
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