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HBM bandwidth and TFLOPS measure different ceilings. HBM3E exceeds 1.2 TB/s per memory stack, while HBM4 exceeds 2.8 TB/s per stack, but an accelerator’s useful speed depends on how much arithmetic each byte of data requires. A low-arithmetic-intensity inference kernel can sit idle on a very high-TFLOPS GPU while waiting for weights, activations or KV-cache data. Conversely, a well-tiled matrix multiply may be compute-bound and gain little from additional bandwidth.
For an AI purchase, compare precision-matched compute, usable HBM capacity, total bandwidth per GPU, inter-GPU links and measured throughput—not a single headline number.
What HBM bandwidth and TFLOPS actually measure
High-bandwidth memory (HBM) is 3D-stacked memory placed close to an accelerator package. Its bandwidth is the rate at which data can be transferred between the stack and the accelerator, normally expressed in decimal terabytes per second: 1 TB/s equals 1,000 GB/s. HBM bandwidth is a memory-side limit.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →TFLOPS means trillions of floating-point operations per second. It is an arithmetic-throughput limit calculated from execution units, clock assumptions and the number of operations performed by each instruction. The figure is meaningful only with a precision attached. FP16, BF16, FP8 and FP4 peaks can be far higher than FP32 or TF32 peaks, and a vendor may publish separate dense and structured-sparse results.
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The roofline model captures the interaction. A kernel’s attainable performance is bounded by the lower of its compute ceiling and its bandwidth ceiling. Arithmetic intensity is the number of operations performed for each byte moved. Low-intensity operations tend to be bandwidth-bound; operations with extensive data reuse can be compute-bound.
HBM3E versus HBM4: the bandwidth curve
| HBM generation | Interface details in Micron’s specification | Bandwidth per stack | What the number means |
|---|---|---|---|
| HBM3E | 1,024 I/O pins; pin speed above 9.2 Gb/s | More than 1.2 TB/s | A single stack’s interface rate, not the total for a GPU |
| HBM4 | 2,048-pin interface; speed above 11.0 Gb/s | More than 2.8 TB/s | More than twice the previous generation’s per-stack figure |
Micron’s HBM3E specification lists more than 1.2 TB/s per stack. Its HBM4 specification lists more than 2.8 TB/s per stack and a 2,048-pin interface. Those are stack-level values. A GPU’s total bandwidth depends on how many stacks are active, the package implementation and the operating rate. Multiplying a stack figure by a stack count is only a first check; the accelerator vendor’s stated per-GPU bandwidth is the number to use in a purchase comparison.
Why a stack number cannot be compared with a GPU number
Suppose a package uses four active HBM3E stacks. A rough arithmetic estimate would be four times more than 1.2 TB/s, or more than 4.8 TB/s, before accounting for the actual interface and implementation. A product page may instead quote a lower or higher validated total, and that validated GPU figure takes precedence. The same issue appears when a vendor describes an eight-GPU platform: a platform total is not interchangeable with one accelerator’s bandwidth.
Record the scope beside every number: per stack, per GPU, per board, or full platform. Also record whether the figure is a theoretical peak, a vendor claim under a specific clock, or a measured application result. Mixing scopes creates an apparently precise but unusable ranking.
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How current accelerator specifications line up
The following figures are vendor-stated specifications, not results from one controlled benchmark. Compute values are theoretical peaks and must be compared at the same precision and sparsity mode.
| Accelerator or platform | Vendor-stated memory | Vendor-stated bandwidth | Compute figures shown by the vendor | Buyer interpretation |
|---|---|---|---|---|
| NVIDIA H100 | HBM | 3 TB/s per GPU | Up to 1 PFLOP TF32 matrix-multiply throughput | A Hopper reference point for both bandwidth and matrix compute |
| NVIDIA H200 | 141 GB HBM3E | 4.8 TB/s | TF32 figures in NVIDIA’s H200 specification table | More capacity and bandwidth than H100; the extra memory does not guarantee faster compute-bound kernels |
| AMD Instinct MI300X | 192 GB HBM3 | 5.325 TB/s | 653.7 TFLOPS TF32; 1,307.4 TFLOPS FP16 | Large capacity and bandwidth, but compare with the same precision and software stack |
| AMD Instinct MI350 platform | HBM3E; up to 2.3 TB across an eight-GPU platform in Micron’s announcement | Up to 8 TB/s per GPU or platform component as stated | Up to 161 PFLOPS FP4 for the eight-GPU platform claim | A platform-level claim; do not compare it directly with one-GPU H100, H200 or MI300X figures |
The H200 row illustrates why capacity and bandwidth should be considered separately from compute. The H200’s 141 GB of HBM3E and 4.8 TB/s bandwidth can reduce weight-loading and cache pressure, yet an already compute-bound kernel may not accelerate proportionally. The MI300X’s TF32 and FP16 values are different operations at different precisions, not two independent measures that can be added together.
Why precision can make TFLOPS comparisons misleading
A TFLOPS headline changes when the data type changes. FP16 or BF16 tensor operations can produce a much larger number than FP32. FP8 and FP4 can produce still larger marketing peaks when the hardware and software support those formats. A table that places an FP4 number beside a TF32 number without labeling the formats makes the faster-looking accelerator appear to have an advantage that may not exist for your model.
Sparsity is another qualifier. Some specifications publish a dense result and a structured-sparse result that assumes zeros are skipped in a supported pattern. Sparse throughput can be valuable when a model and kernel actually use that pattern, but it should not be treated as the dense rate. For each candidate, record:
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- Precision: FP32, TF32, BF16, FP16, FP8 or FP4.
- Dense or sparse execution, including the required sparsity pattern.
- Whether the number is per die, per GPU, per board or for a complete platform.
- The clock or boost assumption behind the peak.
- Whether the result is theoretical or measured on a real model.
When bandwidth determines performance
Bandwidth carries model weights, activations and the key-value (KV) cache used by autoregressive transformers. A low-intensity operation performs relatively few calculations for each byte fetched. If its working set does not remain in cache, tensor cores wait on HBM and utilization falls even though the advertised TFLOPS is high.
Inference can expose this problem during long-context generation, small-batch serving or token-by-token decode, where each new token repeatedly touches weights and KV-cache entries. Increasing HBM capacity can let a model or cache remain on one accelerator, while increasing bandwidth can shorten the time spent streaming that data. Neither benefit is automatic: kernel tiling, cache locality, quantization and batch shape determine the actual traffic.
Training and large-batch matrix multiplication often have more data reuse. A kernel that keeps tiles in on-chip memory can approach its compute ceiling instead of its HBM ceiling. In that case, a faster tensor core path, better clocks or a more efficient kernel may matter more than another increment of external bandwidth.
Evidence that more bandwidth is not always faster
NVIDIA’s TensorRT-LLM H200 discussion reports that its Llama 2 70B execution was “compute performance bound rather than limited by memory bandwidth or communication bottlenecks.” That result is workload-specific, but it demonstrates the decision rule: measure the model and batch configuration you will run instead of assuming the accelerator with the largest TB/s will win.
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The opposite case is also possible. If profiling shows long memory stalls, low arithmetic intensity and a working set that misses cache, a higher-TB/s part can deliver more tokens per second even when its TFLOPS headline is lower. The same accelerator can switch between these regimes as sequence length, batch size, quantization or kernel implementation changes.
A five-step method for choosing an AI accelerator
- Define the exact workload. Specify training or inference, model and parameter size, batch size, sequence length, context length, target latency, throughput objective and concurrency. State whether the model uses FP16, BF16, FP8, FP4 or another format, and whether sparsity is enabled.
- Classify the bottleneck. Use representative profiling to estimate arithmetic intensity and separate bandwidth stalls, tensor-core saturation, cache misses and inter-GPU communication. A roofline plot or kernel counters can show whether the workload is bandwidth-bound, compute-bound or communication-bound.
- Check usable HBM capacity and GPU-level bandwidth. Confirm that weights, runtime buffers and the expected KV cache fit without unwanted host or peer transfers. Then compare the vendor’s total bandwidth per GPU, not a per-stack number. Note how many stacks are active and whether the specification is a peak.
- Evaluate the fabric between GPUs. Multi-GPU inference and training can be limited by interconnect bandwidth or topology even when each GPU has ample HBM bandwidth. Check the actual links, switch layout, collective-communication performance and whether the software maps tensors and experts across devices efficiently.
- Demand measured results and total cost. Require tokens per second, latency percentiles, images per second, time to train or joules per token on your model. Include kernel and library maturity, compiler support, power, cooling, server integration, availability and the cost of the complete system or cloud instance. Treat TFLOPS and TB/s as ceilings, not promises.
How to interpret high TFLOPS with low utilization
Low utilization does not by itself prove that the GPU lacks bandwidth. First identify which unit is idle. A tensor-core utilization counter near zero with high HBM traffic suggests a memory-bound kernel. High tensor utilization with low HBM traffic suggests the arithmetic path is doing the work and additional memory bandwidth may not help. Low utilization on both can indicate launch overhead, poor occupancy, synchronization, CPU input delays or an unsuitable kernel.
Check cache-hit rates and memory transactions, then vary one factor at a time. Increasing batch size can improve arithmetic intensity; reducing precision can increase compute throughput but may alter accuracy; quantization can reduce bytes moved; changing sequence length can change KV-cache pressure. Re-test after each change because a fix can move the workload from one roofline ceiling to the other.
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Capacity, software and interconnect can outweigh raw bandwidth
A model that does not fit in local HBM may incur transfers that overwhelm any nominal bandwidth advantage. Conversely, fitting a larger model or KV cache on one GPU can avoid peer traffic and simplify serving. Capacity is therefore a placement constraint, not merely another performance score.
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Software determines whether the hardware peak is reachable. Verify support for the model’s precision, attention implementation, quantization format, collective libraries, compiler and inference framework. Compare the same optimized kernel path on every candidate; an advertised FP8 or FP4 rate is irrelevant if your framework falls back to a slower format.
For multi-GPU systems, topology matters as much as link speed. A platform-level compute or bandwidth claim may assume a particular eight-GPU arrangement, while a different server wiring can force traffic through slower paths. Ask vendors or cloud providers for the exact topology and benchmark configuration behind any platform result.
Common purchasing mistakes and their fixes
- Ranking by the largest TFLOPS number: Normalize precision, dense or sparse mode and scope before comparing.
- Using stack bandwidth as GPU bandwidth: Multiply only as a sanity check, then use the validated per-GPU specification.
- Assuming HBM4 makes TFLOPS irrelevant: HBM4 raises the memory ceiling; compute-bound kernels still depend on arithmetic throughput.
- Comparing platform and single-GPU figures: Keep an eight-GPU claim separate from one-GPU specifications.
- Ignoring capacity: Verify that weights, activations and KV cache fit under the intended concurrency.
- Trusting a vendor peak as an application result: Obtain measured, model-specific throughput, latency and energy data.
- Neglecting availability and operations: Include server power, cooling, software support, supply and system price in the decision.
What this means for H100, H200, MI300X and MI350 choices
H100 provides a familiar 3 TB/s-per-GPU Hopper baseline and up to 1 PFLOP TF32 matrix-multiply throughput. H200 adds 141 GB of HBM3E and 4.8 TB/s, making it attractive when model capacity or memory traffic is the constraint, but not automatically superior for compute-bound work.
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MI300X combines 192 GB of HBM3 with 5.325 TB/s and publishes 653.7 TFLOPS TF32 or 1,307.4 TFLOPS FP16. Those values should be compared against an NVIDIA candidate at matching precision and with equivalent software optimization.
The MI350 announcement describes an eight-GPU HBM3E platform with up to 2.3 TB of aggregate memory and up to 161 PFLOPS FP4, alongside a bandwidth statement of up to 8 TB/s per GPU or platform component. Because those are platform-level claims, a buyer must verify the exact per-GPU value, topology, precision support and measured application performance before comparing it with a single H100, H200 or MI300X.
Keeping specifications current
Accelerator specifications, firmware, software support and product availability change quickly. Before signing a purchase order or selecting an enterprise HBM GPU platform or cloud instance, re-check every capacity, bandwidth, precision and platform figure in the current vendor documentation. Preserve the access date and label each value as per stack, per GPU or per platform. A specification review is not a substitute for a benchmark on the models and service-level targets you actually operate.
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