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Thermal design for a lidless space-grade FPGA is a system problem: the package’s contact geometry, thermal interface, board, mechanical supports, and spacecraft boundary conditions all affect the heat path. Start with the exact part and package drawing. Then model the assembled design under mission worst-case conditions and validate its margin. Do not assume that AMD Versal XQR and Microchip RTG4 or RT PolarFire packages use the same cooling or mounting approach.

Start with the exact FPGA package and design case

“Lidless” does not define one standard package top or one heatsink arrangement. Before choosing a thermal interface material (TIM) or support structure, identify the exact ordering code and package, then confirm its drawing and mechanical and thermal limits. The die, stiffener, and package surfaces may not be coplanar, and different device families have different vendor-recommended heat paths.

Build a design case that represents the assembled spacecraft hardware, not just the FPGA in isolation. Include:

  • FPGA part number, package, configuration, and expected workload or operating modes.
  • Power estimates for each relevant mode, including the operating condition that drives the thermal worst case.
  • PCB dimensions, materials, stack-up, copper distribution, and mounting details.
  • Nearby heat sources and the thermal paths from the board and cooling hardware into the spacecraft structure.
  • Mission hot and cold conditions and other applicable environmental boundaries.

AMD lists an M-temperature range of −55°C to +125°C for Versal XQR. That is a temperature-grade specification, not a prediction of junction temperature in a particular assembly or proof that the design has adequate thermal margin.

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Choose the heat path for the device family

In vacuum, convection to surrounding air is not a cooling path to rely on. Microchip’s AN5558, published in January 2025, describes heat flow in space applications as conduction and radiation. The board, cold plate, supports, interfaces, and spacecraft structure therefore need to be represented as parts of the thermal system.

Design question AMD Versal XQR lidless guidance Microchip RTG4 and RT PolarFire guidance in AN5558
Primary heat path described Heatsink contacts the die through an interface layer; the sink must account for the package’s die and stiffener geometry. (AMD AM013 and DS946) Cold plate on the back of the system PCB, directly beneath the devices. (Microchip AN5558, January 2025)
Top-side contact or sink The sink needs an island that reaches the die because stiffener height can differ from die height. (AMD AM013) An optional top sink should transfer its load to the frame and PCB, not the FPGA package. (Microchip AN5558, January 2025)
Mechanical support Control attachment pressure: insufficient pressure can impair contact; excessive pressure can damage the device. (AMD AM013) For the covered CCGA mounting, AN5558 recommends metal frames and L-shaped corner brackets. Direct package loading can increase stress under shock and vibration. (Microchip AN5558, January 2025)
Interface or model detail AMD names phase-change materials, thermal grease, and pads; its guidance calls for detailed system modeling. (AMD DS955 and DS946) The cited guidance centers on a rear PCB cold plate and supported mounting arrangement; a comparable top-die TIM recommendation is not stated in AN5558.

These are vendor recommendations for the stated device families and package configurations, not a universal ranking or a rule that one cooling arrangement applies to every FPGA. Follow the exact package documentation. In particular, do not transfer the Microchip rear-cold-plate arrangement to a Versal package, or assume a direct top-sink load is appropriate for an RTG4 or RT PolarFire assembly.

For a Versal XQR die-top interface, design the contact deliberately

Make the heatsink island reach the die

AMD’s AM013 packaging manual explains that the stiffener and silicon die may sit at different heights. A heatsink that rests on the stiffener alone may not contact the die. The sink therefore needs an island positioned and dimensioned to reach the die, based on the selected package drawing and the mechanical stack-up.

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This is a package-specific geometry requirement, not a general instruction to press a heatsink onto any exposed FPGA die. Confirm clearances, relative heights, flatness, and the intended load path for the actual part before releasing the mechanical design.

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Select the TIM using contact and mechanical limits

Even surfaces that appear smooth have microscopic roughness, which reduces the real area of contact. AMD identifies phase-change material, thermal grease, and thermal pads as possible interface types for the lidless die-to-heatsink contact. The appropriate choice depends on the die and heatsink flatness, package pressure limits, and the total thermal contact properties published by the TIM supplier.

Evaluate the selected material in the actual assembly and environment. Supplier data and package limits matter more than a generic claim that a material is “high performance.” Do not treat a consumer TIM’s availability or advertised conductivity as evidence that it is qualified for the spacecraft’s vacuum, service life, or mechanical conditions.

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Model the complete assembly at mission worst case

AMD’s system-level guidance calls for detailed thermal simulation of lidless devices under worst-case environmental conditions, using device models that represent performance under the applicable boundary conditions. An isolated junction-to-ambient figure cannot substitute for analysis of the board, interface, supports, sink or cold plate, and the spacecraft’s conduction and radiation paths.

Use a model suited to the decision

For Versal, obtain the thermal model for the selected device and represent the die, stiffener, heatsink island, interface layer, PCB, and relevant spacecraft paths. AMD states that its device thermal models are available through its registered-customer download site. Its WP563, dated March 10, 2025, describes simplified detailed models for early design iterations and full detailed models for sign-off. The full model includes package features such as substrate traces, interposer, silicon die, and stiffener ring; the simplified model omits detail to reduce simulation burden.

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Use model fidelity appropriate to the question being answered. A simplified model can help compare early concepts, but design sign-off should use a model and assembly representation capable of capturing the important heat paths and contact conditions.

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Run operating and uncertainty cases

Test more than one nominal setup. Vary the inputs that could materially change the predicted temperature or margin, including:

  • Mission boundary temperatures and FPGA power by operating mode.
  • Interface contact assumptions, surface flatness, and attachment pressure.
  • Manufacturing tolerances and relevant material properties.
  • Performance tolerances of any heat transport element used in the design.

AMD specifically calls attention to uncertainty such as manufacturing tolerances, surface flatness, and heat-pipe performance where relevant. For a spacecraft, define boundary conditions that match the actual thermal environment rather than assuming air cooling in vacuum.

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Validate the assembled thermal and mechanical design

Simulation is an input to design decisions, not evidence that a particular board has passed. Compare predictions with suitable component or board measurements and the project’s environmental qualification evidence. The appropriate validation depends on the assembly and mission; the cited vendor documents do not provide test results for your board.

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Keep the mechanical and thermal cases connected during review. A contact arrangement that looks favorable thermally may be unacceptable if it puts load on a package beyond its limits. Conversely, a support structure that protects the package still needs to provide a credible heat path through the board or interface to the spacecraft hardware.

Interpret published package claims narrowly

AMD’s AM013 manual, release July 31, 2026, revision 1.10, says lidless Versal devices can operate up to 10°C cooler at the same power dissipation. Treat that as AMD’s stated package benefit, not a guaranteed temperature reduction for every system. The realized result depends on the surrounding assembly, interfaces, boundary conditions, and implementation.

The same distinction applies to package dimensions. AMD’s Versal XQR portfolio brief lists a 45 mm × 45 mm AI Core package and a 23 mm × 23 mm AI Edge package. Verify the current drawing for the selected part before using those figures for a board or heatsink design.

Quick Recap

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