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To improve a linear regulator’s ripple rejection, first identify the disturbance frequency and choose an LDO that maintains strong PSRR there; then preserve adequate input headroom, follow its capacitor requirements, and add input or feedback filtering if needed. To reduce noise generated inside the regulator, use its noise-reduction pin or a validated feedback network. These are related but different problems: PSRR describes input ripple reaching the output, while output-noise specifications describe noise the regulator generates.

Identify whether the problem is ripple or regulator noise

Power-supply rejection ratio (PSRR) measures how effectively a regulator prevents variations on its input from appearing at its output. It is frequency-dependent, so a single PSRR figure cannot predict performance across all ripple frequencies. Analog Devices notes that a typical LDO may provide as much as 80 dB at 10 Hz but as little as 20 dB at a few tens of kilohertz; check the selected part’s curve at the actual disturbance frequency and operating conditions. See Analog Devices AN-1120.

Internally generated output noise is a separate issue, arising mainly from the reference and error amplifier. A regulator can have good PSRR yet still contribute unwanted noise, or have low intrinsic noise but pass input ripple at frequencies where its PSRR falls. Analog Devices describes filtering the reference and reducing the error amplifier’s noise gain as two main approaches to reducing intrinsic noise in AN-1329.

Use this design sequence

1. Define what must be rejected

Measure the input disturbance before changing components. Record the ripple amplitude and frequency, broadband noise, load-current range, required output-noise measurement bandwidth, and available input-to-output voltage margin. Include the expected temperature range and any allowable thermal rise. A narrow switching-frequency spur may call for a different remedy from broadband noise or low-frequency ripple.

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2. Select an LDO using its PSRR curve

Compare PSRR at the frequency of the disturbance, not just at a convenient low-frequency point or a headline maximum. Check that the curve applies to your load current, input-output differential, output capacitor and other stated conditions. Keep VIN − VOUT comfortably above dropout: TI cautions that PSRR and transient response degrade as this difference approaches the dropout voltage in the TPS7A8101 datasheet.

When comparing parts, also consider output noise over the bandwidth that matters to your circuit, load-transient response, startup time, quiescent current, capacitor and stability requirements, package availability, heat, and sensitivity to layout. A quoted RMS noise value is meaningful only with its measurement bandwidth and test conditions.

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3. Meet the input and output capacitor requirements

Place the specified input bypass capacitor near the regulator’s input pin. It can improve transient response, noise rejection and ripple rejection, but it does not substitute for checking PSRR at the relevant frequency. Capacitor value, dielectric, bias-dependent capacitance, ESR and placement all matter.

Requirements differ by device. For example, the TI TPS730 datasheet calls for a nearby ceramic input bypass capacitor and specifies a 2.2 µF minimum output capacitor in common configurations; it requires 4.7 µF when VOUT is below 1.8 V or when feed-forward compensation is not used. The TPS7A8101 datasheet recommends a nearby 0.1–1 µF low-ESR input capacitor and a 4.7 µF or larger ceramic output capacitor, with X5R or X7R dielectric and maximum ESR below 1 Ω. Treat these as model-specific examples, not universal LDO values.

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4. Reduce internally generated noise at the reference or feedback node

If the regulator includes an NR or BYP pin, use the datasheet-specified capacitor and a low-leakage component. The pin typically filters reference noise; an arbitrary capacitor or value can alter startup or stability, so do not assume that larger is always better.

For an adjustable regulator, a validated RC network in the feedback path can reduce noise and improve low-frequency PSRR. Analog Devices reports 15–20 dB of PSRR improvement from 10 Hz to about 20 kHz in tested examples in AN-1329. TI also describes a feed-forward capacitor across the upper feedback resistor as a way to improve noise, stability, load response and PSRR on adjustable regulators; follow the specific part’s design guidance in TI’s feed-forward capacitor application note.

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Filtering can slow startup because the relevant node takes longer to settle. In Analog Devices’ examples, a 10 nF network increased startup from about 600 µs to 6 ms, while 1 µF increased it to about 600 ms. These are example results, not a general prediction for every LDO or network; verify startup in your design.

5. Add input filtering or cascade regulators if the remaining ripple demands it

A damped RC or LC filter ahead of the LDO can attenuate input ripple, particularly at frequencies where the regulator’s own rejection is weak. Account for the filter’s voltage drop and source impedance, and check damping, inductor resonance, current rating and interaction with the regulator’s stability. An undamped filter can create a resonant peak instead of reducing the disturbance.

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Cascading LDOs can add rejection, but the result depends on both devices, their operating conditions and the interstage network. Analog Devices gives an example of a MAX8875 followed by a MAX8867 achieving 70 dB PSRR at 100 kHz with 1 µF capacitors in “Improved Power-Supply Rejection for Linear Regulators”. This is a specific example, not a guaranteed cascade result. Check that the first regulator leaves enough voltage for the second, and account for dissipation, startup sequencing and stability.

6. Keep layout parasitics under control

Place input, output and NR/BYP capacitors close to their respective pins, with short, wide return paths. Keep the feedback node away from switching nodes and high-current ground paths. At high frequencies, capacitor equivalent series resistance and inductance, trace inductance and return-path coupling can undermine the result. Analog Devices discusses the impact of output-capacitor ESR/ESL and board layout on high-frequency PSRR in AN-1120.

7. Validate across real operating conditions

Test the assembled design rather than relying only on typical curves. Sweep the ripple frequency and load current, check input-output headroom and temperature, and use the actual output capacitor under DC bias. Measure output noise with a stated bandwidth and suitable probing technique. Also check startup, load transients, loop stability, thermal dissipation, and conducted or radiated coupling from nearby circuitry.

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What a capacitor can—and cannot—fix

There is no universal capacitor value that reduces every LDO’s noise. An output capacitor is primarily part of the regulator’s required operating network; an NR/BYP capacitor filters the reference on regulators designed for one; and feedback capacitors or RC networks apply only to suitable adjustable parts. An input filter targets ripple entering the regulator. Choose the component and value from the exact datasheet or a validated application circuit, then confirm the effect at the frequencies and bandwidth relevant to your design.

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Likewise, do not equate PSRR in decibels with an output-noise RMS figure. PSRR is a frequency-specific ratio for input disturbance rejection. RMS output noise integrates noise over a specified bandwidth and test setup. Analog Devices’ AN-83 includes 20 µVRMS output-noise examples for the LT1962 and LT1763, but those example figures should not be treated as universal values outside the stated measurement conditions: Analog Devices AN-83.

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