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To convert interlaced HDTV to progressive video in real time, an FPGA must reconstruct the missing lines in each field and deliver pixels at the output timing your display or downstream pipeline expects. Bob is the simplest, low-memory option; weave preserves detail in static scenes but can comb during motion; motion-adaptive processing switches methods by image region and needs more buffering and logic. AMD documents a 1080i60-to-1080p60 configuration, but the exact memory, latency, and device fit depend on the selected core and video format.
What deinterlacing does to 1080i video
Interlaced video represents an image as two fields: one contains one set of alternating lines and the other contains the remaining lines. The fields are captured at different times, so combining them is not always equivalent to joining two halves of the same still image. A progressive display, by contrast, expects complete frames. A deinterlacer reconstructs the lines absent from each field and emits progressive frames.
Be precise about timing labels. Video modes described as “1080i60” are often discussed in terms of a 60-field-per-second cadence, while a frame consists of a pair of fields. Vendor mode names and interface timing conventions should be checked against the actual signal. AMD’s Video Processing Subsystem guide documents 1080i60 input to 1080p60 output as an example without a frame-rate change; that is a supported configuration example, not a guarantee that every FPGA design, input format, or system can sustain it.
Choose the reconstruction method
| Method | How it fills missing lines | Moving edges | Still-scene detail | Storage and trade-off |
|---|---|---|---|---|
| Bob (line doubling or vertical interpolation) | Uses lines from the current field to create the missing lines. | Avoids the combing caused by joining fields captured at different times; motion can appear to bob vertically. | Can lose vertical detail because each output frame is built from one field. | Can use line buffers rather than external frame buffers, making it the simplest low-memory choice. |
| Weave | Combines lines from adjacent fields. | Moving objects can show comb-like horizontal teeth where the two fields differ. | Retains full vertical detail when the scene is static. | Requires access to another field; its detail advantage depends on motion being absent or negligible. |
| Motion-adaptive | Detects moving and still regions, using bob-like interpolation for motion and weave-like reconstruction for static areas. | Generally avoids weave combing in regions identified as moving. | Preserves more detail in regions classified as still than bob alone. | Needs temporal context, buffering, motion analysis, and more control logic; exact cost depends on the core and configuration. |
Motion-adaptive is not a single fixed algorithm. AMD lists selectable choices including line doubling, weave, vertical temporal linear interpolation, vertical temporal median, median, and bilinear interpolation. Intel/Altera also documents a high-quality Sobel-edge interpolation option and optional 3:2 and 2:2 cadence detection for film-originated material. These options are not necessarily equivalent across vendors.
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Estimate memory before choosing an FPGA core
There is no defensible universal frame-memory number without the raster, pixel format, bit packing, stride, buffering scheme, and algorithm. A bob implementation may need only internal line buffers; weave needs access to lines from neighboring fields; motion-adaptive processing needs temporal samples to compare fields. AMD documents a motion-adaptive subsystem that may use three field buffers, but that does not establish a byte count for every configuration or prove that three complete uncompressed frames must be stored.
For a first estimate, calculate storage from the actual buffer dimensions and memory representation:
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Buffer bytes = stored pixels × bytes per stored pixel
Then multiply by the number of buffers actually allocated by the chosen IP and add any stride padding or alignment required by its memory interface. For example, 4:2:2 and 4:4:4 chroma sampling do not have the same storage per pixel, and 8-, 10-, or 12-bit samples may be packed differently by an implementation. Confirm whether the core stores fields or full frames, whether samples are packed or padded, and whether any buffers can be shared. Use the generated configuration and memory-controller requirements—not a generic “1080i needs X megabytes” rule—as the final sizing basis.
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Plan the FPGA video pipeline
- Confirm the signal: identify active dimensions, field cadence and order, blanking/timing conventions, and whether the source is genuinely interlaced rather than progressive content carried in an interlaced format.
- Select the reconstruction mode: choose bob when low buffering and predictable motion behavior matter most; choose weave only where motion-related combing is acceptable; choose motion-adaptive when balancing moving-edge handling and static detail is worth the added resources.
- Match format and interface: verify chroma sampling, component layout, bit depth, clocking, and back-pressure or valid/ready behavior for the selected video interface. Microchip documents both AXI4-Stream and native video interfaces, as well as RGB444, YUV444, and YUV422 at 8-, 10-, and 12-bit depths for its bob core.
- Set field order correctly: configure which field arrives first according to the input standard. AMD register documentation distinguishes NTSC/480i ordering from PAL/HD/3G ordering; a mismatch can make temporal reconstruction incorrect.
- Budget storage and timing: map the core’s field or line buffers to available memory resources, account for memory bandwidth, and check the full pipeline latency against downstream timing requirements.
- Validate with motion and still detail: inspect moving diagonals and horizontal edges for combing, static fine patterns for lost detail, and motion for vertical bobbing. Verify the output timing and frame cadence at the actual interface.
- Close with device-specific implementation reports: check BRAM, logic, clock frequency, memory use, and latency after synthesis and implementation for the target FPGA and selected configuration.
Compare available vendor IP by the implementation you need
| Vendor core | Documented options or emphasis | Details to verify for a specific design |
|---|---|---|
| AMD/Xilinx Video Processing Subsystem | Field-buffered motion-adaptive processing and configurable choices including bob, weave, temporal interpolation, median, and bilinear methods; the guide gives a 1080i60-to-1080p60 example. | Buffer allocation, device-specific resource use, latency, supported formats, and exact configured algorithm behavior. |
| Intel/Altera Deinterlacer / Deinterlacer II | Bob, weave, motion-adaptive processing, high-quality edge interpolation, and optional 3:2/2:2 cadence detection. The documented parameter set lists a maximum generated progressive height of 1080 pixels. | Whether the documented height and options apply to the selected IP generation, device, and parameter configuration; also check memory and timing reports. |
| Microchip Deinterlacer IP | Real-time bob processing with internal line buffers; AXI4-Stream or native interfaces; AXI4-Lite control; RGB444, YUV444, and YUV422 at 8-, 10-, or 12-bit depths. | Whether bob meets image-quality needs, exact latency, throughput, device fit, and how the chosen interface handles timing. |
| Lattice Deinterlacer IP | Weave, bob, intra motion-adaptive, and inter motion-adaptive algorithms, with documented explanations of their artifact trade-offs. | Supported formats, buffer requirements, latency, resource use, and availability for the specific FPGA and toolchain. |
Published cross-vendor figures for FPGA utilization, latency, and image quality are not established here, so these cores cannot be ranked fairly on those measures. Licensing, device compatibility, toolchain support, and the exact generated-IP configuration should be checked in the relevant vendor documentation before committing to an architecture.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can an FPGA convert 1080i60 to 1080p60 in real time?
Yes, this is a practical FPGA video-processing task, and AMD documents 1080i60 input converted to 1080p60 output with no frame-rate change. “Real time” means the pipeline accepts the live input cadence and produces the required progressive output continuously; it does not mean zero latency. Temporal processing may buffer fields before it can make a decision, and the actual delay depends on the algorithm, memory system, and downstream pipeline. Confirm the target device’s timing and resource reports and measure end-to-end latency in the intended configuration.
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