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Choose the chip only after you have measured the workload. Start with the model’s architecture and size, precision, prompt and output lengths, concurrency, latency targets, and deployment limits. Calculate usable memory—including weights, KV cache, runtime workspace and safety headroom—before comparing compute specifications. Then benchmark the remaining candidates with the same model, software stack and traffic pattern.
For online generative-AI serving, memory bandwidth, software compatibility and predictable latency often matter more than a headline TOPS or FLOPS number. A high-bandwidth GPU or TPU can be the right answer for a large cloud service; a CPU, NPU or compact GPU may be better for a low-power edge function. There is no universally fastest or cheapest inference chip.
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1. Define the inference workload before looking at chips
Two deployments can serve the same model and still need different hardware. An interactive chatbot with short prompts, long generated answers and strict time-to-first-token targets behaves differently from an offline summarization job that processes large batches. AWS Prescriptive Guidance makes this distinction explicit: prompt length, response length, concurrency and latency objectives change infrastructure requirements.
Record the variables that determine capacity
| Workload input | What to record | Why it changes the choice |
|---|---|---|
| Model | Architecture, parameter count, supported operators and tokenizer | Determines memory footprint and whether the accelerator can execute the graph. |
| Precision | FP16, FP8, INT4, NVFP4 or another supported format | Changes weight memory, arithmetic throughput and output accuracy. |
| Sequence lengths | Typical and maximum prompt tokens; typical and maximum output tokens | Prompt prefill and token-by-token decoding stress different resources, while longer context increases KV-cache demand. |
| Traffic | Requests per second, arrival pattern, batch size and peak concurrency | Determines queueing, batching efficiency and the number of chips required. |
| Service objectives | Time to first token, inter-token latency, end-to-end latency, throughput and availability | A chip optimized for maximum throughput may fail an interactive latency target. |
| Deployment | Power budget, cooling, physical space, connectivity, serviceability and cloud topology | Can eliminate otherwise capable hardware before performance testing. |
Use measured or production-like distributions rather than a single average. Keep separate p50, p95 and p99 targets when tail latency matters; a system that looks fast on average can still violate a user-facing SLO during bursts.
#1 Best Overall
- Memory Size: 16 GB GDDR6 ECC.
- Memory Bus Width: 128-bit.
- Memory Bandwidth: 200 GB/s.
- CUDA Cores: 1280.
- Peak Single Precision floating point performance: 18 Tflops (GPU Boost Clocks).
2. Check usable memory before compute
Memory capacity is the first elimination test. Count model weights, activations, the KV cache, framework and compiler workspace, communication buffers and a safety margin for fragmentation and traffic spikes. Use usable accelerator memory, not the number printed on a product page.
What consumes memory
- Weights: The model parameters at the deployed precision. Lower-bit quantization reduces this component, but only if the runtime and kernels support the chosen format.
- KV cache: Stored keys and values for active sequences. It grows with context length, batch size, number of layers and concurrent requests, so an interactive service can exhaust memory even when the weights fit comfortably.
- Activations and workspace: Temporary tensors, attention buffers, compiler workspaces and runtime allocations. Their size depends on architecture, sequence length, batch and backend.
- Headroom: Capacity reserved for allocator fragmentation, variable requests, scheduling and fail-safe operation. Deploying at the physical limit leaves no room for real traffic.
A practical AWS rule illustrates the consequence: if a deployment requires 90 GB of memory, a single accelerator with less usable memory is eliminated regardless of its advertised throughput. That rule applies before a benchmark because no software optimization can make an over-capacity single-chip deployment reliable.
Separate prefill from decoding
Prompt prefill processes many input tokens together and is generally more compute-bound. Sequential decoding generates one token at a time and is often limited by moving weights and KV-cache data, making memory bandwidth and latency critical. Google’s TPU guidance therefore emphasizes high HBM bandwidth and substantial on-chip SRAM for online serving, while compute density and throughput per dollar become more important for batched prefill and offline inference.
Make a memory worksheet
- Measure the model’s weight size at each precision you are considering.
- Estimate KV-cache growth at the maximum context, target concurrency and expected batch.
- Add activations, framework workspace, communication buffers and runtime allocations observed in a representative test.
- Reserve explicit safety headroom for fragmentation and traffic spikes.
- Reject any candidate whose usable memory is below the resulting requirement, even if its compute specification is attractive.
Do not compare “VRAM” or HBM capacity in isolation. Partitioning, system-reserved memory and multi-chip communication can reduce what the model actually receives.
3. Understand what compute and bandwidth numbers do—and do not—tell you
Peak FLOPS or TOPS describes an arithmetic ceiling under specific data types and operation shapes. Inference performance can instead be limited by memory bandwidth, math bandwidth, kernel launch latency, synchronization or input/output movement. NVIDIA’s performance guidance describes these as separate possible bottlenecks and notes that Tensor Core efficiency depends on operation dimensions aligning with supported multiples.
Use a roofline view
A roofline analysis compares the arithmetic work of an operation with the bytes it must move. A low-arithmetic-intensity decode step can be bandwidth-bound even on a chip with enormous theoretical compute. A large, well-batched matrix multiplication can approach the compute ceiling. Run this analysis for the actual model and sequence lengths; do not infer the bottleneck from the chip’s marketing peak.
Interpret bandwidth correctly
Advertised HBM or memory bandwidth is not the same as sustained bandwidth available to your model. Kernel access patterns, cache reuse, contention, quantization layout and inter-chip traffic all affect delivered performance. Google announced 7.37 TB/s of HBM bandwidth per chip for its Ironwood TPU in 2025. That is a dated vendor specification, not a promise that every model will use 7.37 TB/s.
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- TOPS may refer to a particular precision and sparsity assumption that your model does not use.
- Unsupported operators can force execution onto another processor or use slower fallback kernels.
- Small or irregular tensor dimensions can leave matrix engines underutilized.
- Input and output transfers, tokenization and scheduling can dominate end-to-end latency.
- A lower-peak chip with better memory behavior or a more mature backend can deliver more useful tokens per second.
4. Select the processor family that fits the workload
| Processor family | Strong fit | Questions and limitations |
|---|---|---|
| GPU | Broad framework support, varied models, high-throughput serving and portable inference tooling. | Can require substantial power and cooling; verify usable memory, interconnect topology, partitioning and kernel support. |
| TPU | Cloud serving or batch workloads that map well to Google’s software stack and benefit from high-bandwidth, scalable infrastructure. | Confirm that the model, operators, compiler and precision formats are supported; account for system topology and cloud availability. |
| NPU | Always-on, low-power edge functions when the device SDK supports the model graph. | Operator and quantization coverage can be narrower; unsupported layers may run on the CPU or GPU and reduce efficiency. |
| CPU | Small or sequential models, preprocessing, orchestration and fallback paths where simplicity or low setup cost matters. | Large, highly parallel models may not meet throughput or latency goals without significant optimization or distributed execution. |
When a GPU is the practical default
Choose a GPU first when you need broad model portability, mature inference frameworks and a large ecosystem of optimized kernels. NVIDIA’s TensorRT and Triton examples illustrate how compiler transformations and serving systems target latency and throughput. The benefit is not the GPU label by itself; it is the combination of supported operators, runtime maturity, memory capacity and deployment tooling.
When a TPU is sensible
Consider a TPU when the model and framework map cleanly to Google’s stack and your workload benefits from scalable cloud infrastructure. Online serving tends to favor high bandwidth and large on-chip memory, while batch inference can favor compute density and throughput economics. Validate the complete software path before committing.
Rank #2
- 3328 optimized CUDA Cores, 7.99 TFLOPS
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When an NPU is enough
An NPU can be sufficient for a compact, supported model running continuously at the edge, where power and heat matter more than peak throughput. Intel describes NPUs as low-power engines in heterogeneous CPU/GPU/NPU systems. Treat the device SDK’s operator list, compiler behavior and fallback rules as hard requirements; an NPU that executes only part of the graph may not improve the total pipeline.
Where a CPU still belongs
CPUs remain useful for low-latency sequential processing, request handling, tokenization, preprocessing, postprocessing and graceful fallback. For a small model or low request rate, a CPU-only service can be operationally simpler than adding an accelerator. Measure it against the same SLOs rather than assuming an accelerator is automatically cheaper.
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5. Treat software compatibility as a go/no-go requirement
A chip is useful only when your model can run on it with an acceptable accuracy, latency and maintenance profile. Check compatibility before purchasing hardware or reserving cloud capacity.
Compatibility checklist
- Framework and compiler versions supported by the accelerator.
- Every model operator, attention variant and activation function mapped to an optimized kernel.
- Tokenizer, preprocessing and postprocessing paths supported in the production container.
- FP16, FP8, INT4, NVFP4 or other required precision formats available end to end.
- Driver, firmware, runtime and container versions pinned and reproducible.
- Monitoring for utilization, memory, temperature, power, queueing, errors and token latency.
- Multi-tenant isolation or partitioning, including whether a feature such as MIG is supported on the selected GPU.
- Upgrade, rollback and security support for the expected service lifetime.
Google recommends vendor-neutral models and tooling so that cross-accelerator comparisons remain possible. Keep an unoptimized reference implementation for correctness checks, then compare optimized backends against it after every compiler, driver or quantization change.
6. Set explicit latency and throughput objectives
Latency and throughput are different objectives. Define each metric before benchmarking:
- Time to first token (TTFT): Request arrival to the first generated token. It includes queueing and prompt processing.
- Inter-token latency (ITL): Time between generated tokens after the first. It shapes how responsive streaming feels.
- End-to-end latency: Request arrival until the complete response, including all generated tokens.
- Throughput: Output tokens per second, requests per second or both, reported with the concurrency that produced the result.
- Concurrency: Number of in-flight requests. Higher concurrency can improve utilization while increasing queueing and tail latency.
- Availability and error rate: Whether the system meets its latency target during normal and peak traffic without rejected or failed requests.
“Fastest” is meaningless without these definitions. A chip that maximizes offline tokens per second may be the wrong choice for a chat service with a strict p95 TTFT and ITL target.
7. Choose precision with an accuracy budget
FP16, FP8, INT4 and NVFP4 can reduce memory use and potentially increase throughput, but they are not interchangeable. Lower precision changes numerical error, calibration requirements, kernel availability and sometimes supported context or batch shapes.
A safe precision process
- Establish a quality baseline with the original model and reference precision.
- Quantize or convert one format at a time using a representative calibration set.
- Measure task accuracy, safety behavior, refusal behavior and output quality—not only perplexity.
- Verify that the selected backend executes the format without hidden dequantization or CPU fallbacks.
- Retest TTFT, ITL, end-to-end latency, throughput, memory and energy at target concurrency.
- Set a documented maximum accuracy delta and reject formats that exceed it.
The best precision is the lowest-memory format that stays within your quality budget and has reliable production kernels. A theoretical gain disappears if conversion, fallback or accuracy remediation costs more than the saved accelerator capacity.
8. Benchmark candidates under identical conditions
Google’s accelerator benchmarking guidance recommends a sequence of microbenchmarks, roofline analysis and model benchmarks, followed by normalized measures such as tokens per second per chip or per dollar. NVIDIA’s reference-architecture guidance similarly calls for endpoint-level latency, throughput, token, concurrency and benchmark reports.
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Build a reproducible test matrix
- Freeze the artifact: Use the same model weights, tokenizer, quantization, prompt set and output-generation settings.
- Freeze the software: Record framework, compiler, runtime, driver, firmware, container and serving-server versions.
- Match the hardware path: Document accelerator type, host CPU, system memory, network mode, interconnect, storage and topology.
- Reproduce traffic: Replay realistic prompt and output-length distributions, arrival patterns, batch sizes and concurrency levels.
- Control cache state: State whether weights and kernels are warm, whether the KV cache is reused, and how startup and compilation time are handled.
- Warm up and repeat: Discard startup outliers only when you report warm-service results separately; run enough repetitions to calculate tail percentiles.
- Collect system data: Capture latency, throughput, errors, accelerator utilization, memory use, power and temperature.
- Normalize the result: Report useful output per chip, per watt, per hour and per dollar at the same quality and SLO.
Report more than a single score
| Result | Minimum context to publish |
|---|---|
| TTFT and ITL | Percentile, prompt/output distribution, concurrency and cache state. |
| End-to-end latency | Generated-token count, queueing policy and whether network time is included. |
| Throughput | Tokens or requests per second, batch, concurrency and error rate. |
| Memory | Weights, KV cache, peak allocation and reserved headroom. |
| Power and energy | Measurement boundary, utilization and whether host and cooling power are included. |
| Cost | Accelerator, host, storage, networking, cooling, orchestration and utilization assumptions. |
Do not combine results from different model versions or traffic profiles into one ranking. If a candidate cannot run the exact workload, label the result as a compatibility failure rather than substituting a smaller model and calling it comparable.
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9. Account for edge and cloud deployment constraints
Edge inference
At the edge, power, cooling, enclosure size, connectivity and serviceability can dominate the decision. A lower-power GPU, CPU or NPU may be preferable when the device must run continuously without active cooling or reliable network access. NVIDIA’s resource guidance positions the A2 as an example of a lower-power GPU for edge inference; more demanding workloads can require larger A30- or A100-class systems. These are workload-dependent examples, not a universal product ranking.
Check local storage for model updates, secure boot and rollback, remote monitoring, failure recovery and the time required to replace a field device. Measure performance at the device’s sustained thermal state, not immediately after a cold start.
Cloud serving
Cloud deployments add interconnect, topology, storage, autoscaling and network costs. A multi-chip configuration can provide capacity that one chip cannot, but communication and synchronization may reduce useful throughput. Include accelerator idle time while scaling, model-loading time, regional availability and the cost of reserved capacity or on-demand bursts.
For large services, decide whether to scale up with a larger accelerator or scale out with more replicas. Scale-out can improve fault isolation and independent autoscaling; scale-up can reduce coordination overhead. Benchmark both at the concurrency and availability target.
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Accelerator hourly price is only one line item. Include the host CPU and memory, networking, storage, orchestration, monitoring, cooling, power, licensing, engineering effort and expected utilization. Divide the total by accepted output tokens or successful requests, not raw peak throughput.
Useful economic measures
- Cost per successful request: Total operating cost divided by completed requests at the required quality and SLO.
- Cost per output token: Total cost divided by generated tokens, with input-token charges or processing costs included where applicable.
- Energy per output token: Measured accelerator and host energy divided by useful generated tokens.
- Capacity at the SLO: Maximum sustainable throughput before the chosen latency percentile or error target is breached.
- Utilization-adjusted cost: Cost under realistic average and peak utilization, including idle capacity reserved for availability.
A high-throughput chip can lose on cost if it is lightly utilized, while a less powerful system can lose if it needs many replicas or violates latency targets. Compare complete system economics under the same traffic and quality assumptions.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.11. Put vendor claims in context
NVIDIA has reported that its systems were more than 100 times faster than CPU-only systems in its summary of MLPerf 2.0 results from 2022. That is NVIDIA’s description of that benchmark, not a guarantee for every model, precision, software version or CPU baseline.
Google stated in 2025 that Ironwood offered nearly two times improved power efficiency versus its prior generation. The comparison is Google’s stated generational claim; verify the measurement boundary and workload before using it in a purchase model.
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12. A practical decision workflow
- Write the SLO: Set TTFT, ITL, end-to-end latency, throughput, concurrency, availability and error targets.
- Describe the traffic: Capture prompt and output distributions, peak arrival rate, batch behavior and cache reuse.
- Build the memory model: Include weights, KV cache, activations, workspace, buffers and safety headroom.
- Eliminate by capacity: Reject chips that cannot hold the model and active requests with the required margin.
- Filter by software: Confirm operators, precision, compiler, runtime, monitoring and partitioning support.
- Select processor families: Keep GPUs, TPUs, NPUs or CPUs only when they fit the deployment environment and model stack.
- Benchmark survivors: Use identical artifacts, versions, traffic, concurrency and cache conditions.
- Measure system economics: Record latency percentiles, throughput, errors, utilization, power, energy and total cost.
- Stress the failure modes: Test long contexts, burst traffic, cold starts, model reloads, thermal throttling and partial failures.
- Choose with a scorecard: Select the lowest-risk option that meets quality, SLO, power, availability and cost requirements—not the chip with the largest peak number.
13. Common mistakes and how to correct them
Choosing by TOPS or FLOPS alone
Why it fails: The model may be bandwidth-bound, use unsupported dimensions or spend time in data movement.
Correction: Measure sustained bandwidth, kernel utilization, TTFT and ITL on the real model.
Checking only weight memory
Why it fails: KV cache and workspace grow with context and concurrency.
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Benchmarking at one request
Why it fails: Single-request latency says little about queueing, batching or tail behavior at production concurrency.
Correction: Test a sweep of concurrency and report both latency percentiles and sustainable throughput.
Ignoring software fallbacks
Why it fails: An unsupported operator or quantization format can move part of the graph to a CPU or slower path.
Correction: Inspect execution traces and verify that the intended kernels run end to end.
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Comparing incompatible benchmarks
Why it fails: Different model revisions, output lengths, drivers or cache states produce incomparable numbers.
Correction: Freeze the artifact and environment, then publish the complete test conditions.
Optimizing peak utilization instead of user experience
Why it fails: Maximum utilization can create queueing and violate latency SLOs.
Correction: Optimize capacity at the required percentile latency and availability, leaving room for bursts.
14. Example choices by workload pattern
Always-on edge classifier
Start with an NPU or CPU if the model is small, supported and latency requirements are modest. Consider a compact GPU when the graph needs broader operator coverage or higher parallel throughput. Prioritize sustained power, passive cooling, local storage, SDK support and recovery over peak TOPS.
Interactive large-language-model service
Begin with memory capacity and KV-cache sizing, then evaluate high-bandwidth GPUs or TPUs whose software stack supports the model. Set separate TTFT and ITL targets, test long contexts and peak concurrency, and compare scale-up with multiple replicas. Precision changes should be accepted only after quality and backend tests.
Offline batch generation
Batch prefill and high utilization can make compute density and throughput per dollar more important than single-request latency. Compare GPUs and TPUs using the same batch and sequence distribution, and include storage, host and interconnect costs in the total.
Small sequential or fallback workload
A CPU can be the most practical choice when the model is compact, traffic is low or the service needs a dependable fallback path. Benchmark it against the accelerator alternatives at the actual request rate rather than assuming that adding a chip improves economics.
Bottom line
The right AI inference chip is the one that holds your model and live cache, executes it through a compatible software stack, meets latency and throughput SLOs at realistic concurrency, and does so within power and total-cost limits. Use memory and compatibility to eliminate impossible options, bandwidth and compute analysis to understand the bottleneck, and controlled end-to-end benchmarks to choose among the survivors.
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