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The right foundry is the one that can manufacture your complete AI system—not merely offer the smallest advertised process node. Start with the workload, die and package architecture, memory, thermal limits, volume and launch date. Then qualify foundries against the exact process design kit (PDK), proven IP, electronic-design-automation (EDA) flow, capacity, yield, advanced packaging, test, geography and contractual protections your program requires.
Shortlist suppliers only after they confirm those requirements in writing. A structured request for quotation (RFQ) should cover non-recurring engineering (NRE), masks, wafer pricing, allocation, lead time, yield reporting, package and test charges, quality grade, security, export controls, change notification and remedies if schedule or yield targets are missed.
1. Begin with the chip and system you must deliver
Foundry selection is a systems decision. Two AI accelerators with similar compute throughput can require very different manufacturing solutions because of memory bandwidth, die size, package power, reliability grade or production volume. Freeze a written requirements baseline before discussing nodes or suppliers.
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- Model class: State whether the device targets training, inference, recommendation, vision, language, signal processing or a mixed workload. Record representative model sizes and operator mix.
- Numerical precision: Specify FP32, BF16, FP16, INT8, INT4 or other formats, including accumulation precision and sparsity assumptions.
- Throughput and latency: Define operations per second, tokens or images per second, batch size, tail-latency target and the performance required at the intended thermal limit.
- Memory: Quantify on-die SRAM, external DRAM or HBM capacity, bandwidth, error-correction requirements and expected memory traffic. These figures often determine package technology and I/O more than the compute array does.
Physical, electrical and commercial constraints
- Die and package: Estimate die area, reticle utilization, number of chiplets, interconnect standard, package dimensions, substrate or interposer needs and board-level interfaces.
- Power and cooling: Set typical and worst-case power, voltage domains, junction-temperature limits, heat-spreader or liquid-cooling assumptions and allowable leakage.
- Volume: Separate engineering wafers, qualification lots, pilot production and annual high-volume demand. Include ramp shape rather than one total number.
- Qualification: Identify commercial, industrial, automotive, defense or other grade; required operating life; reliability tests; traceability; and any country-specific certifications.
- Schedule: Set tape-out, first silicon, package qualification, customer sampling and volume-launch dates. Include time for a possible respin.
- Geography: List where design, wafer fabrication, assembly, test and final shipment may occur, together with data-residency, export-control and business-continuity constraints.
These inputs become pass/fail gates. A foundry that cannot meet the package thermal path or production geography is unsuitable even if its transistor density looks attractive.
#1 Best Overall
![Arduino® UNO™ Q 4GB [ABX00173]- Hybrid Board, Qualcomm Dragonwing QRB2210 microprocessor (MPU) & STM32U585 Microcontroller(MCU), AI Vision, Voice, IoT, Robotics, Linux Debian OS, Wi-Fi 5, USB-C](https://m.media-amazon.com/images/I/51cl4xygwGL._SL160_.jpg)
- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
- AI & Linux Capabilities: Unlocks AI-powered vision and sound solutions; runs Linux Debian OS for coding in Python and supports the Arduino ecosystem with libraries and Sketches; quick start with Arduino App Lab.
- Advanced Features: Equipped with 4 GB LPDDR4 RAM, 32 GB eMMC built-in storage, ideal for single-board computer (SBC) mode, running multiple simultaneous high-level processes, more complex AI or ML models, extensive logs. Dual-band Wi-Fi 5 (2.4/5 GHz), Bluetooth 5.1, and high-speed headers for vision, audio, and display peripherals.
- Seamless Expansion & Connectivity: Features the classic UNO form factor for shields compatibility, an 8x13 LED matrix, and a Qwiic connector for easy expansion with Modulino nodes; power and connect via the USB-C connector.
- Intended Use & Development: The perfect platform for prototyping robotics or IoT projects, empowering innovators with a unified development experience to mix Arduino Sketches, Python scripts, and containerized AI models in a single interface.
2. Match the design to a specific process and PDK
“3 nm,” “5 nm” and similar labels are useful starting points, not interchangeable specifications. Ask each supplier for the exact process family, PDK revision, design rules, libraries, memory options, analog support, I/O voltage range and production status that apply to your design.
What to verify in the PDK
- Revision and maturity: Record the PDK release, supported EDA-tool versions, known limitations, change history and planned revisions between design start and tape-out.
- Standard-cell libraries: Confirm high-performance, low-power, high-density and multi-voltage libraries, characterization corners, electromigration limits and usable operating frequencies.
- SRAM and memory compilers: Check available bit-cell options, density, redundancy, repair, voltage domains, compiler qualification and yield data for the sizes your accelerator needs.
- Analog and I/O: Verify high-speed SerDes, PCIe or other host links, clocking, power-management devices, analog interfaces, electrostatic-discharge structures and package escape requirements.
- Third-party IP: Obtain a list of licensable and silicon-proven CPU, interconnect, security, interface, memory and chiplet IP. Clarify ownership, indemnity, maintenance and porting responsibilities.
- Design-rule and sign-off flow: Confirm physical-verification decks, extraction, timing, power integrity, thermal analysis, formal checks and the exact sign-off criteria accepted for tape-out.
- Reference silicon: Request anonymized evidence of production designs using the same process, major IP blocks and package technology. “Available” IP is not equivalent to IP proven at your required frequency, voltage and temperature.
TSMC publicly describes a portfolio ranging from 3 nm FinFET to 0.18 micron and emphasizes process-proven IP and design-ecosystem support. The relevant question for your project is not the breadth of that portfolio, but whether the exact node and IP combination has evidence at your die size, power and volume.
Node choice: performance versus execution risk
A newer node can reduce energy per operation or increase transistor density, but it may also bring higher masks, tighter design rules, fewer mature IP options and greater schedule sensitivity. A mature node can simplify analog, I/O, yield and supply, while requiring a larger die or more chiplets. Compare total system cost and delivery risk rather than transistor density alone.
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3. Evaluate the design ecosystem, not just the fab
Your team will interact with a network of foundry engineers, IP vendors, EDA providers, package houses, assembly and test sites and design-service partners. The quality and availability of that network often determine whether a first tape-out succeeds.
TSMC Open Innovation Platform
TSMC’s Open Innovation Platform (OIP) organizes technology, design enablement, ecosystem partners and a Design Center Alliance. Ask which alliance members have current experience with your process, package, memory and region; who owns schedule coordination; and how escalation works when an IP or EDA issue blocks sign-off.
Samsung Foundry and SAFE
Samsung Foundry lists logic and specialty processes for AI, machine learning and high-performance computing. Its SAFE ecosystem covers PDKs, libraries, IP, design support, packaging and cloud services. Confirm the specific SAFE partners available to your project, whether their deliverables are qualified on the selected process, and which support is included in the quoted engagement.
Intel Foundry
Intel says its foundry supports ARM, RISC-V, x86 and custom ASIC architectures and combines IP, EDA, process nodes, advanced packaging and assembly and test services. That breadth can be valuable for a systems-of-chips design, but you still need process-specific evidence, package capacity, schedule commitments and clear responsibility boundaries among design, wafer and assembly teams.
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- Who is the named technical program manager from architecture through volume production?
- How many tape-outs on this exact process and package have the proposed engineering team supported?
- Which IP blocks are production-proven, and what are the documented errata or operating restrictions?
- What response time and escalation path apply to PDK, design-rule, yield and test issues?
- Can the foundry coordinate EDA, IP, substrate, interposer, assembly and test suppliers under one change-control process?
4. Make packaging and test first-class requirements
AI accelerators increasingly use chiplets, stacked memory and heterogeneous integration. Package bandwidth, power delivery and thermal resistance can limit system performance before the logic die does.
Rank #2
- Dual-Brain Hybrid Power: Combines the Qualcomm Dragonwing QRB2210 MPU (Quad-core Arm Cortex-A53 @ 2.0 GHz CPU, Adreno GPU, AI acceleration) and the real-time, low-power STM32U585 MCU for advanced applications like object recognition, voice commands, and motion detection.
- AI & Linux Capabilities: Unlocks AI-powered vision and sound solutions; runs Linux Debian OS for coding in Python and supports the Arduino ecosystem with libraries and Sketches; quick start with Arduino App Lab.
- Advanced Features: Equipped with 2 GB LPDDR4 RAM, 16 GB eMMC built-in storage, ideal to develop in PC-connected mode, running the OS, Python scripts, and basic network services (SSH) without a demanding GUI or heavy multitasking; great for lightweight AI and memory-optimized TinyML applications, needing local storage for basic OS and core libraries. Dual-band Wi-Fi 5 (2.4/5 GHz), Bluetooth 5.1, and high-speed headers for vision, audio, and display peripherals.
- Seamless Expansion & Connectivity: Features the classic UNO form factor for shields compatibility, an 8x13 LED matrix, and a Qwiic connector for easy expansion with Modulino nodes; power and connect via the USB-C connector.
- Intended Use & Development: The perfect platform for prototyping robotics or IoT projects, empowering innovators with a unified development experience to mix Arduino Sketches, Python scripts, and containerized AI models in a single interface.
Package architecture
Define whether the design needs a monolithic package, 2.5D interposer, 3D stacking, fan-out, bridge or another structure. Confirm package dimensions, substrate layers, bump pitch, warpage limits, power-delivery network, signal-integrity modeling, HBM generation and stack count. Require early package co-design models; waiting until after logic sign-off can force a costly redesign.
Samsung describes integrated 2D and 3D package solutions. Treat that as an option to investigate, then verify the exact package, memory supplier compatibility, thermal model, assembly location and production capacity for your program.
Thermal and mechanical validation
- Obtain a package-level thermal-resistance model at your expected power density and cooling method.
- Check heat-spreader, lid, underfill, warpage and board-attachment constraints across operating temperature.
- Validate HBM placement, power noise, clock distribution and signal margins with the intended substrate and interposer.
- Ask how package changes are qualified and how long a substrate or assembly-site change takes.
Known-good die and final test
Chiplet systems need a defined known-good-die (KGD) flow. Specify wafer probe coverage, defect screens, electrical limits, burn-in, traceability, die-binning rules and the data passed from wafer test to assembly. Intel notes that increasing chiplet counts create a need for advanced test services that identify known-good die before final assembly. Ask for the test insertion points and reject criteria, not merely a statement that “advanced test” is available.
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5. Validate capacity, yield and schedule with evidence
Public supplier pages generally do not provide comparable customer-specific yield or guaranteed allocation. Those facts must be validated directly and protected contractually.
Capacity and allocation
- Request committed wafer starts by quarter, technology family and geography, with assumptions for engineering, ramp and steady-state production.
- Ask how capacity is prioritized during shortages, what minimum purchase commitments apply and whether unused allocation can roll forward.
- Confirm wafer diameter, lot size, cycle time, queue policy and the lead time for mask, wafer, package and test orders.
- Document second-source or contingency options, including whether the design can port to another process or assembly site.
Yield and excursion management
Request historical yield ranges for the same process family and a comparable die-size and design class, while recognizing that an average across unrelated products is not predictive. Define how yield is measured, when data is reported, what constitutes an excursion, who leads root-cause analysis and what corrective-action timeline applies. Include wafer-sort fallout, package yield and final-test yield; optimizing only wafer yield can hide losses later in the flow.
Schedule realism
Build a critical-path schedule covering PDK readiness, IP qualification, design reviews, mask release, wafer fabrication, wafer sort, package assembly, KGD screening, final test, reliability qualification and customer sampling. Obtain dates for both normal flow and a respin. A first-silicon date without package and test dates is not a product schedule.
6. Compare commercial, security and operational risk
Foundry economics extend well beyond the wafer quote. Compare total cost of ownership and the consequences of delay.
Rank #3
- Single core ARM Cortex-A7 32-bit core, integrated with NEON and FPU
- Built in Micro's self-developed 4th generation NPU, with high computational accuracy and support for mixed quantization of int4, int8, and int16. Among them, int8 has a computing power of 0.5 TOPS and int4 has a computing power of up to 1.0 TOPS
- Built in self-developed 3rd generation ISP3.2, supports 4 million pixels, and supports various image enhancement and correction algorithms such as HDR, WDR, and multi-level denoisin
- It has powerful encoding performance, supports intelligent encoding, adapts to save bit rates according to the scene, and saves more than 50% of the bit rate compared to conventional CBR mode, making the captured images high-definition, smaller in size, and doubling the storage space
- The design with built-in RISC-V MCU supports low-power fast startup, 250ms fast capture, and simultaneous loading of AI model library, enabling facial recognition to be completed within 1 second
| Area | What to request in the RFQ | Why it matters |
|---|---|---|
| NRE and masks | Engineering fees, mask-set price, reticle revisions, package development and test-program charges, with payment milestones. | Mask and development costs can dominate a low-volume AI ASIC and make a respin financially decisive. |
| Wafer economics | Price by volume tier, wafer size, tested-wafer versus bare-wafer basis, scrap treatment and validity period. | A low nominal wafer price may exclude probe, sort, engineering lots or inflation adjustments. |
| Commitments | Minimum annual volume, take-or-pay terms, cancellation rights, allocation rules and expedite pricing. | Protects both sides when demand forecasts change. |
| Quality | Qualification standards, reliability reports, traceability, corrective-action process and audit rights. | Required grade and failure reporting differ by market and customer. |
| Security and IP | Confidentiality, access controls, employee screening, secure design-data transfer, IP indemnity and ownership of improvements. | AI designs, models and package data are valuable targets and may be subject to customer restrictions. |
| Export controls | Country-of-origin analysis, licensing responsibility, restricted-party screening and notification of rule changes. | Controls can affect design access, equipment, wafer shipment and end-customer delivery. |
| Business continuity | Site redundancy, disaster recovery, geopolitical exposure, alternate assembly and test locations and recovery-time objectives. | Reduces dependence on one region, facility or subcontractor. |
| Change control | Notice periods and approval rights for PDK, process, materials, equipment, fab, package or test changes. | Uncontrolled changes can invalidate qualification or alter performance and yield. |
| Remedies | Service levels, credits, rework, replacement lots and termination rights for missed schedule, yield or quality commitments. | Converts operational promises into enforceable protection. |
7. Use a repeatable foundry-selection process
- Freeze the requirement baseline. Record workload, precision, throughput, latency, memory, die area, power, package, volume, qualification and launch date. Mark assumptions and sensitivity ranges.
- Issue a technical pre-qualification questionnaire. Ask only for process families, PDK status, IP, package, test, capacity, yield evidence, quality, security and geography relevant to the design.
- Hold architecture workshops. Review floorplan, memory hierarchy, chiplet partition, HBM, thermal path, I/O and test strategy with each shortlisted supplier.
- Request a structured RFQ. Require identical response templates for NRE, masks, wafers, package, test, lead time, allocation, engineering support, payment terms and remedies.
- Run design-rule and IP feasibility. Have your internal design and verification leads confirm that the PDK, libraries, compilers, interfaces and sign-off flow support the intended implementation.
- Audit manufacturing and test. Review relevant fab, assembly and test sites, quality systems, traceability, security controls, KGD flow and contingency plans.
- Score and stress-test the options. Model delayed ramp, lower yield, higher package cost, export restrictions, a respin and a demand surge. Reject any option that fails a non-negotiable gate.
- Negotiate before design lock. Put allocation, data delivery, change notification, yield reporting, confidentiality, IP protection and remedies into the master agreement and statements of work.
- Use staged commitments. Tie mask release, engineering lots and volume reservations to PDK maturity, IP sign-off, package readiness and agreed technical milestones.
8. A practical scoring model
Use weighted scoring to make trade-offs visible, then apply hard gates for requirements that cannot be compromised. Adjust weights to your product; the example below is a starting structure rather than a universal ranking.
| Criterion | Suggested weight | Evidence to score |
|---|---|---|
| Process, PDK and IP readiness | 20% | Exact PDK revision, libraries, compilers, EDA flow, silicon-proven IP and reference designs. |
| Package, memory and thermal fit | 20% | 2D/2.5D/3D capability, HBM compatibility, substrate, interposer, thermal model and package capacity. |
| Yield, capacity and schedule | 20% | Comparable yield evidence, wafer allocation, cycle time, ramp plan and excursion response. |
| Test and quality | 10% | KGD, wafer probe, final test, reliability qualification, traceability and audit results. |
| Economics | 15% | NRE, masks, wafer, package, test, minimum commitments and cost sensitivity to yield. |
| Security, geography and continuity | 10% | IP controls, export exposure, site redundancy and alternate manufacturing paths. |
| Support and governance | 5% | Named team, escalation, change control, reporting and contractual remedies. |
Score each criterion with documented evidence, not sales confidence. Set a minimum score for every critical category and mark claims that remain unverified. A supplier with a lower weighted total may still be the correct choice if it is the only one that passes a mandatory package, qualification or geography requirement.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.9. Supplier-specific diligence questions
For TSMC
- Which OIP and Design Center Alliance partners are available for the selected process, package and region?
- What current PDK revision, SRAM compilers, HBM interfaces and high-speed I/O IP are production-proven for the intended design class?
- How are wafer allocation, package coordination and escalation managed across TSMC and external assembly or test providers?
For Samsung Foundry
- Which logic or specialty process best fits the AI workload, memory and power target, and what is its current production status?
- Which SAFE ecosystem members can support architecture, physical design, package co-design and cloud-based development?
- For an integrated 2D, 2.5D or 3D solution, where are substrate, interposer, assembly and test performed, and what capacity is committed?
For Intel Foundry
- How will ARM, RISC-V, x86 or custom-ASIC elements be supported in the selected process and EDA flow?
- Which parts of the IP, process, advanced packaging and Intel Foundry ASAT stack are included in the program?
- How are chiplet KGD screening, final assembly, test data and responsibility boundaries handled across the foundry and customer teams?
10. Common selection mistakes and recovery actions
Choosing the smallest advertised node
Failure: The design team selects a node before checking SRAM, analog, I/O, package and IP maturity.
Recovery: Re-run architecture and cost models on at least one mature alternative. Include die area, leakage, masks, schedule and yield—not only peak compute.
Accepting unqualified yield claims
Failure: A supplier quotes a broad process-family yield that does not represent your die size, memory or package.
Recovery: Request comparable historical ranges, define measurement methods and require lot-level reporting, excursion handling and remedies in the contract.
Leaving package and test until the end
Failure: The logic die is complete, but HBM, interposer, thermal resistance, KGD or final-test capacity is unavailable.
Recovery: Freeze package and test requirements during architecture, run package co-design, and reserve assembly, probe and final-test capacity before tape-out.
Rank #4
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- 【USER‑FRIENDLY VISUAL & PLUG‑AND‑PLAY】2” TFT‑SPI color screen shows real‑time chat; modular design, no extra wiring, ready to use after setup.
- 【FULL LEARNING SUPPORT】45 programmable GPIOs, rich interfaces, online web tutorials, free technical support for beginners & developers.
Relying on a single verbal schedule
Failure: “First silicon” is treated as the launch date.
Recovery: Contract milestone dates for PDK, masks, wafers, sort, package, test, reliability and customer samples, with a respin plan and escalation path.
Ignoring jurisdiction and continuity
Failure: Export restrictions, site concentration or a subcontractor change interrupts delivery.
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Recovery: Map every design, wafer, assembly and test location; obtain licensing responsibilities in writing; and qualify an alternate site or portable contingency where practical.
11. How the major options differ at a high level
| Foundry | Publicly described strengths relevant to AI ASIC selection | Items you still must verify |
|---|---|---|
| TSMC | Broad process portfolio; process-proven IP and design ecosystem; OIP technology, design enablement, ecosystem partners and Design Center Alliance. | Exact PDK and IP maturity, allocation, package and HBM path, assembly/test responsibility, yield evidence and contractual remedies for your program. |
| Samsung Foundry | Logic and specialty processes aimed at AI/ML and HPC; SAFE resources for PDKs, libraries, IP, design support, packaging and cloud services; integrated 2D/3D package solutions. | Selected-node production status, ecosystem partner fit, package capacity, thermal and HBM implementation, yield, schedule and geography. |
| Intel Foundry | Support stated for ARM, RISC-V, x86 and custom ASIC architectures; a systems-foundry stack spanning IP, EDA, process nodes, advanced packaging and ASAT; chiplet and KGD test emphasis. | Exact process and PDK readiness, package and ASAT capacity, test coverage, allocation, yield, commercial terms and cross-site governance. |
Intel stated that 3 trillion semiconductor units were shipped globally in 2024, including 1.4 billion AI chips. That is Intel’s stated industry figure, not an independent market estimate, and it should not be used as a substitute for supplier-specific capacity evidence.
12. Make the final decision
Select the foundry that provides the strongest evidence for the entire path from design enablement to tested, qualified product at your required volume and location. In practical terms, that means an exact PDK and IP fit; a package, memory and thermal plan that has been modeled and can be manufactured; credible capacity, yield and schedule commitments; complete wafer-to-final-test coverage; and contracts that protect your design, data, supply and launch.
Do not award the program on node name, a headline wafer price or a generic ecosystem brochure. Require written answers, comparable evidence, staged commitments and a contingency plan. The best foundry for a custom AI chip is the one that can demonstrate—not merely promise—that your architecture can reach repeatable, qualified production.
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