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Choose a chip foundry by matching a qualified process platform to your product—not by selecting the smallest node number or a fab that owns the newest lithography scanner. Start with performance, power, area, voltage, analog/RF, memory, reliability, package, volume and product-life requirements. Then verify the foundry’s process design kit (PDK), intellectual property (IP), critical-layer lithography, yield evidence, capacity, cost, geography and supply-continuity options.
A “3nm” or “2nm” label is a generation name, not a universal physical measurement. Two nodes with the same label can have different transistor architectures, design rules, libraries, SRAM density, voltages, backside or interconnect options and measured performance. EUV and High-NA EUV can simplify critical-layer patterning, but scanner ownership alone does not prove that your exact product can achieve acceptable yield, cost or delivery dates.
What a process node actually tells you
Process-node names are useful shorthand for a technology generation, but they are not comparable rulers. A foundry’s advertised node may summarize a family of process variants with different transistor options, metal stacks, design rules and target applications. A nominally smaller node can improve logic density or energy efficiency while offering fewer analog, high-voltage, embedded-memory or reliability options than a larger specialty process.
Compare the complete process platform: transistor architecture, contacted-poly pitch, metal pitches, standard-cell libraries, SRAM bit-cell options, operating-voltage range, leakage targets, interconnect stack, available memories, reliability qualification and package support. Your own place-and-route results, circuit simulations and test-chip data are more meaningful than a headline node comparison.
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Why “3nm versus 2nm” is not a universal contest
Different foundries may use FinFET, gate-all-around (GAA) nanosheet, fully depleted silicon-on-insulator (FD-SOI), planar or specialty devices under their node labels. Design rules and library choices can erase a theoretical density advantage if they force larger cells, more restrictive routing or extra voltage domains. A process that is excellent for a mobile application processor may be a poor fit for a precision sensor, automotive controller or radio-frequency front end.
Use measured product targets
Translate the product brief into measurable limits: maximum active power, standby leakage, frequency at a defined voltage, die-area ceiling, SRAM capacity, analog noise, RF gain or linearity, thermal envelope, package dimensions and required lifetime. Ask every candidate foundry to model the same workload and test conditions. Otherwise, “better PPA” (performance, power and area) is only a marketing comparison.
Start with a one-page foundry requirement
Before contacting fabs, write a one-page requirement that separates hard gates from preferences. Include:
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- Electrical: frequency, throughput, active and idle power, leakage, supply rails, clocking, voltage tolerance and memory bandwidth.
- Physical: maximum die size, pad count, reticle constraints, thermal design power, package outline and allowed process-voltage-temperature corners.
- Circuits: digital logic, SRAM, nonvolatile memory, analog, RF, high-voltage, image-sensor or power devices required on the same die.
- Reliability: qualification standard, operating temperature, electromigration limits, mission duration, radiation tolerance and failure-rate targets.
- Commercial: prototype date, annual wafer demand, ramp profile, product lifetime, acceptable wafer price, mask budget and inventory policy.
- Supply: approved manufacturing regions, export-control constraints, security requirements, second-source expectations and package/test geography.
This document prevents a team from optimizing for a node that cannot satisfy voltage, memory, analog or lifecycle requirements.
Classify the design before comparing foundries
Classify the chip into the technology family that best reflects its dominant risk. The classification determines which process capabilities matter most.
Leading-edge logic
High-performance CPUs, GPUs, AI accelerators and network processors may justify the newest FinFET or GAA platform when frequency, energy per operation or density pays for the additional masks, design effort and wafer cost. Confirm that the required standard cells, SRAM compiler, high-speed interfaces and package are production-qualified, not merely demonstrated.
Mature logic
Control processors, connectivity controllers and industrial devices often gain more from low nonrecurring cost, broad IP, stable yields and long availability than from maximum density. A mature digital platform can also simplify voltage options and physical design.
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Analog, RF, high-voltage and mixed-signal
Radio transceivers, power-management ICs, display drivers and sensor interfaces depend on device matching, passive components, isolation, high-voltage devices, RF models and specialized metal stacks. A larger node with a proven specialty module can outperform a leading-edge logic process at the system level.
FD-SOI and embedded-memory designs
FD-SOI can offer body-bias control, low leakage and useful analog or RF behavior. Embedded nonvolatile memory, secure elements and always-on domains may make a differentiated platform preferable to a minimum-node logic process.
How major published roadmaps should be interpreted
Public capability statements are useful for creating a shortlist, but they are not a commitment that your design is eligible, qualified or capacity-backed. Ask for the exact process version, wafer location, ramp status, design rules and commercial access.
| Foundry or platform | Published capability relevant to selection | What you must verify |
|---|---|---|
| Samsung Foundry | Samsung describes a portfolio from 180nm to 2nm and beyond, covering GAA, FinFET, FD-SOI, planar and specialty technologies. Its logic material identifies 7nm as the point at which EUV lithography was introduced and lists mass-production milestones for several nodes. | Which node variant contains the needed voltage, memory, analog/RF and reliability modules; the qualified PDK and IP; actual wafer site, yield, capacity and customer-access terms. |
| Intel Foundry | Intel describes geographically distributed wafer fabrication, Intel 18A, Intel 3, Intel 16, advanced packaging and test, and the first 2nm-class process node manufactured in North America. | Whether the required product can use the stated node, where wafers will be made, current ramp status, external-customer onboarding, package/test flow and export or security restrictions. |
| GlobalFoundries FDX Fusion | GF describes an FD-SOI platform targeting seven-nanometer-class digital performance with RF and embedded nonvolatile-memory features for edge and Physical AI applications. Initial manufacturing is planned for Dresden, demonstrator silicon is targeted for early 2027 and a PDK release is planned for mid-2027. | These are forward-looking dates, not guaranteed production availability. Confirm PDK release, qualification, wafer pricing, volume capacity and whether the needed IP and package are ready when your tape-out occurs. |
| TSMC and other EUV-capable foundries | The IEEE IRDS 2022 Executive Summary reports EUV supporting accelerated logic scaling at TSMC and Samsung. | Do not infer equal design rules, density, yield or commercial access from EUV use. Request process-specific PDK restrictions, critical-layer plans, capacity and measured PPA. |
Statements such as Samsung’s “from 180nm to 2nm and beyond” and Intel’s “first 2nm-class process node manufactured in North America” describe each company’s published scope. Treat them as starting points for diligence, not as interchangeable specifications.
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Evaluate lithography at the critical layer
Lithography determines how patterns are printed, but the relevant question is not simply whether a fab has EUV. Ask which layers of your exact process use deep ultraviolet (DUV), EUV or High-NA EUV; what overlay and critical-dimension control are qualified; how masks are made; and what the patterning strategy does to cycle time, defectivity and cost.
DUV and multiple patterning
DUV tools remain important across mature and advanced processes. When a feature is too dense for a single exposure, multiple patterning can divide it across masks and process steps. That may increase mask count, alignment sensitivity, process complexity and cost. A mature node may avoid these penalties because its design rules are less aggressive.
Production EUV
EUV can replace some multiple-patterning steps on critical layers and support continued logic scaling. The IEEE International Roadmap for Devices and Systems (IRDS) 2022 Executive Summary recorded 31% growth in EUV-lithography-system shipments in 2021, production tools with 0.33 numerical aperture and 0.55-NA tools under development. These figures provide industry context from 2022; they do not establish today’s price, capacity or yield for a particular foundry.
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High-NA EUV
On September 7, 2026, Intel and ASML reported High-NA EUV use in high-volume manufacturing at Intel Foundry and more than one million wafers processed across qualification, research and development, and selected production layers. They also discussed mask format, stitching, overlay, throughput and availability work. This is significant evidence of industrial progress, but it does not mean every High-NA process is open to every customer or that every layer of a product uses High-NA.
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- Which critical layers use EUV, High-NA EUV or DUV?
- What are the overlay, critical-dimension and defectivity limits for those layers?
- Are the mask format, stitching and design rules supported by the current PDK and EDA flow?
- What yield, cycle-time and tool-availability evidence exists for your product class and volume?
- Are EUV or High-NA masks included in the quoted mask schedule and cost?
Design enablement is a qualification gate
A theoretically capable process is unusable if the design environment is immature. Request the current PDK release and check whether it includes:
- Design-rule manual, layer definitions, extraction decks and sign-off verification.
- Standard-cell libraries across the needed voltage and performance options.
- Characterized SRAM, register-file and embedded-memory compilers.
- Analog, RF, high-voltage and passive-device models where applicable.
- Interface IP for PCIe, USB, Ethernet, memory and security functions required by the product.
- Certified flows for synthesis, place and route, timing, power, signal integrity, physical verification and reliability analysis.
- Reference designs, shuttle programs, application engineers and design-service support.
Ask for PDK revision history and known restrictions. A late design-rule change can force mask edits, rerouting or a new tape-out. Confirm that third-party IP licenses permit your geography, product market and expected lifetime.
Compare manufacturability, not just transistor density
Yield learning, capacity and cycle time determine whether a chip can ship. Request wafer-sort and final-test data for a comparable design class, while recognizing that a foundry may not disclose customer-specific results. Clarify:
- Expected first-silicon yield range and the conditions under which it was measured.
- Ramp milestones, committed monthly wafer starts and allocation rules during shortages.
- Typical wafer cycle time, queue time, engineering-lot timing and rework policy.
- Reticle-size limits, maximum die size and known yield penalties for large dies.
- Defect-density learning, reliability-screen results and qualification status.
- Package assembly, wafer-level packaging, bumping, test coverage and burn-in capacity.
Packaging can erase a process advantage. Advanced logic may require a specific interposer, chiplet interface, thermal solution or high-bandwidth-memory package. Evaluate wafer fabrication and assembly/test as one supply chain, including logistics between regions.
Model total cost of ownership
Do not compare wafer quotes alone. Build a five- to ten-year model, using the product lifetime rather than the foundry’s promotional period. Include:
| Cost element | Questions to quantify |
|---|---|
| Masks and tape-outs | How many masks, reticles and engineering lots are required? What is the cost of a design spin? |
| Wafers and yield | What is the wafer price at the committed volume, and how does good-die yield change cost per shipped unit? |
| Design enablement | What are PDK, IP, EDA, shuttle and design-service fees, and which licenses recur annually? |
| Packaging and test | What package, assembly site, test time, burn-in and substrate costs are required? |
| Migration and second source | What engineering effort is needed to move to another node or foundry if supply is interrupted? |
| Inventory and logistics | How much safety stock, regional warehousing and transport capacity are needed to meet the service level? |
Public sources do not provide a complete comparable table of current prices, minimum volumes, guaranteed capacity or customer eligibility. Obtain those terms under a commercial agreement and record whether each number is a quote, estimate, one-time charge or recurring commitment.
Leading-edge or mature node? Use a decision matrix
| Requirement | Leading-edge platform tends to fit when… | Mature or specialty platform tends to fit when… |
|---|---|---|
| Performance and energy | Frequency, throughput or energy per operation directly determines product value and the design can exploit the density. | System performance is limited by analog, memory, package or software rather than logic gates. |
| Analog/RF and voltage | The advanced platform includes proven device models and all required voltage options. | Precision, RF, high-voltage or isolation devices are central to the product. |
| Memory | Validated SRAM density and compiler options meet capacity and yield targets. | Embedded nonvolatile memory or unusual memory size dominates the design. |
| Volume and cost | High volume amortizes masks, IP and design effort, and the PPA gain supports the price. | Moderate volume, long life or low mask budget makes stable cost more valuable. |
| Lifecycle | A short consumer life can tolerate rapid node transitions and capacity competition. | Industrial, automotive or infrastructure products need long availability and controlled changes. |
| Supply resilience | Multiple qualified sites, package sources and migration plans exist. | A regional or specialty fab offers stronger continuity and less allocation risk. |
A larger node is not a compromise if it lowers total system cost, improves analog behavior, shortens qualification or remains available for the entire product life. Conversely, a mature node is a poor choice when its leakage, density or interface limits prevent the product from meeting its fundamental specification.
Follow a practical qualification sequence
- Freeze the product brief. Record PPA, voltage, memory, analog/RF, reliability, package, volume and lifetime targets, including acceptable tolerances.
- Classify the technology. Decide whether the design is leading-edge logic, mature logic, specialty analog/RF, FD-SOI, high-voltage, embedded-memory or a mixed-technology device.
- Create a shortlist. Select process platforms that satisfy hard electrical and device requirements before considering geography or price.
- Request enablement data. Obtain the current PDK, IP catalog, design-rule manuals, library characterization, EDA certification, shuttle options and package/test flows.
- Interrogate lithography. Ask which lithography is used on each critical layer of the exact process version and request evidence for overlay, defectivity, yield and mask strategy.
- Run representative design work. Implement a block or shuttle test vehicle using your actual memories, interfaces, analog blocks and voltage domains. Measure PPA, routability, timing closure and rule violations.
- Audit manufacturing. Verify wafer site, qualification status, cycle time, capacity, ramp evidence, engineering-lot dates and allocation policy.
- Model total cost. Combine masks, wafers, yield, IP, design migration, packaging, test, logistics and inventory under conservative and optimistic scenarios.
- Review legal and security constraints. Check export controls, data-handling rules, trusted-foundry requirements, regional manufacturing limits and IP indemnities.
- Approve a continuity plan. Decide whether a second source, compatible process, chiplet partition or redesign path justifies its cost, and preserve the documentation needed to execute it.
Questions to put in the foundry request for information
Process and lithography
- What is the exact process designation and revision offered to an external customer?
- Which layers use DUV, EUV or High-NA EUV, and what patterning restrictions apply?
- What are the qualified voltage, temperature, reliability and metal-stack options?
- Which features are production-qualified versus roadmap or demonstrator status?
Enablement and support
- What PDK version, standard-cell libraries, SRAM, analog/RF models and interface IP are available today?
- Which EDA tools and sign-off decks are certified, and how are rule changes communicated?
- What shuttle, prototype and engineering-lot programs are available?
Manufacturing and business
- Where will wafers be processed, and can the site and package source be changed without requalification?
- What capacity, cycle time, yield evidence and ramp commitments apply to the forecast volume?
- What are the mask, wafer, packaging, test, minimum-volume and cancellation terms?
- How long will the process remain orderable, and what notice is provided for changes or end of life?
Common selection mistakes and how to correct them
Choosing the smallest advertised node
Failure: The design misses analog, memory, voltage, yield or cost targets. Correction: Require a process-to-requirement matrix and representative PPA results before approval.
Treating node names as physical measurements
Failure: A nominally smaller node produces no system advantage because libraries, wiring or SRAM dominate. Correction: Compare density, frequency, leakage and area using the same design and workload.
Equating scanner ownership with product readiness
Failure: EUV or High-NA capacity exists, but the critical layer, PDK, yield or volume slot is not qualified. Correction: Request layer-level evidence and a written production path for your exact process.
Ignoring packaging and test
Failure: The die meets PPA targets but cannot obtain the required substrate, interposer, thermal solution or test capacity. Correction: Qualify fabrication, assembly and test together.
Trusting roadmap dates as commitments
Failure: A tape-out depends on a PDK or fab ramp that slips. Correction: Tie schedules to released PDKs, qualified silicon and contractual capacity; maintain a fallback process.
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Leaving lifecycle planning until production
Failure: A long-lived product becomes dependent on a short-lived node or a single region. Correction: Negotiate lifecycle terms early and document a second-source or migration route.
Examples of sound choices
High-throughput digital accelerator
If energy per inference and throughput determine revenue, evaluate an advanced logic platform with proven SRAM, high-speed interfaces, advanced packaging and enough wafer allocation. Compare complete accelerator benchmarks, not node labels, and include mask amortization and package thermal limits.
Industrial sensor hub
If the chip combines low-power control, precision analog, RF and embedded nonvolatile memory, a specialty or FD-SOI platform may reduce risk. Verify sensor models, body-bias or leakage behavior, memory endurance, temperature qualification and long-term availability before rejecting a larger node.
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Automotive or infrastructure controller
Reliability, process change control, qualification evidence, secure supply and a decade-scale lifecycle may outweigh density. A mature node with established high-voltage devices, package sources and regional capacity can be the stronger business decision.
Make the final decision with explicit gates
Approve a foundry only when it passes all non-negotiable gates:
- The process meets electrical, physical, memory, analog/RF and reliability requirements with margin.
- The PDK, IP, libraries and EDA flow are released and usable for the planned tape-out.
- Critical-layer lithography, yield, capacity and cycle time are evidenced for the exact process version.
- Wafer, package and test economics meet the product’s lifetime business case.
- Geography, export, security and logistics requirements are satisfied.
- Lifecycle commitments and a credible second-source or migration plan cover the product’s risk tolerance.
Use the smallest node only when its measured system benefit exceeds the added mask, design, yield, packaging and supply risk. Otherwise, select the process platform that can be designed, qualified, manufactured and supported for the entire life of the product.
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