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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallA small 6502 computer needs a 65C02-family processor, writable SRAM, and ROM or EEPROM holding startup code. Those are the three core chips—not necessarily the complete IC count: many practical designs also need a separate address-decoding chip. Start with an explicit memory map, make the ROM visible at the reset vector, and bring the system up one subsystem at a time.
What “three ICs” means in a practical 6502 build
The three essential functions are processing, writable memory, and nonvolatile startup storage. A CPU, SRAM, and ROM/EEPROM cover those functions. They do not automatically make a working three-package circuit: a documented design may add a 74LS00 quad NAND gate to generate memory selects, bringing the total to four IC packages. A programmable logic device or other discrete logic can also handle decoding.
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Unless you have a complete schematic proving the selected parts can generate valid chip-select signals without another IC, treat “three IC” as the core CPU/RAM/ROM count and list decoding logic separately. Confirm the active-high or active-low sense of every select pin in the exact memory and logic datasheets. Never assume that two parts with similar names use the same polarity.
Parts and architecture to plan before wiring
CPU
A WDC W65C02S is one 65C02-family option. Its datasheet, dated February 16, 2024, specifies a 16-bit address bus and an 8-bit data bus, providing 65,536 bytes of address space. Check the exact part suffix, package, pinout, supply range, and speed grade; a listing that says only “6502” may refer to a different NMOS or CMOS variant. The W65C02S datasheet is the authority for that processor’s electrical and timing requirements.
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SRAM and ROM
SRAM holds writable data such as zero-page variables, stack contents, and program data. A documented example uses a 62256, a 32K × 8 SRAM; a design need not map all of its capacity. ROM or EEPROM holds startup code and must supply the reset vector. One example uses a 28C256, while the Crab Apple design maps an 8 KiB EEPROM region at $E000–$FFFF. The capacity of the chip and the range selected by the decoder are separate decisions: your programmed image and decoding must agree.
Address decoding and support components
A 74LS00 is one documented simple decoder option; a programmable logic device can provide a more flexible map. Also plan for a regulated supply compatible with every selected device, a clock source, reset circuitry or switch, local bypass capacitors, prototyping board or breadboard, and access to an EEPROM programmer. Sockets can make component replacement easier.
A secondary build guide recommends 0.1 μF bypass capacitance at each IC and bulk capacitance at the supply entry as common practice, but treat those as starting suggestions, not universal values. Check the selected components’ datasheets and your board layout. Similarly, do not copy a voltage, clock rate, or programming procedure from another build without confirming compatibility.
Choose a memory map that serves the reset vector
The CPU presents an address on A0–A15 and transfers bytes on D0–D7. RWB indicates whether the processor is reading or writing. During a read, only the intended memory or I/O device should drive the shared data bus. During a write, SRAM should accept data only for intended addresses and write cycles; ROM output must remain disabled.
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Two published designs illustrate different valid choices. They are examples, not a standard map to copy blindly:
| Example | RAM | ROM | Other mapping |
|---|---|---|---|
| Stackable 6502 | $0000–$3FFF (16 KiB selected) | $8000–$FFFF (32 KiB) | ACIA at $5000–$5FFF; VIA at $6000–$6FFF; project warns that $7000–$7FFF conflicts. Stackable project |
| Crab Apple | $0000–$7FFF (32 KiB) | $E000–$FFFF (8 KiB ROM image region) | UART occupies $8000–$DFFF in its loosely decoded implementation. Crab Apple project |
For the W65C02S, reset reads the vector at $FFFC (low byte) and $FFFD (high byte). ROM therefore has to respond at both addresses after reset, and those two bytes must encode the entry address your program is intended to run. If the ROM is mapped at $E000–$FFFF, for example, place and program the image accordingly. Vector bytes are little-endian: the low byte comes first at $FFFC, followed by the high byte at $FFFD. A map, decoder truth table, and ROM image are one coordinated design—not independent choices.
Wire and bring up the computer in stages
- Plan the exact parts and map. Record the full part numbers and draw the address map. Mark ROM at $FFFC–$FFFD, then make a truth table for RAM, ROM, and any I/O selects across reads and writes. Verify each device’s select polarity and the decoder’s logic from the relevant datasheets before wiring.
- Verify the power rails before inserting ICs. Check supply polarity, regulated voltage, and ground continuity. Fit the bypass capacitors required for your parts and layout. Confirm that the CPU, SRAM, ROM, and any logic device can all operate at the chosen supply voltage.
- Establish clock and reset. The W65C02S datasheet recommends an external oscillator for PHI2. Keep RESB low until VDD is at operating voltage and for at least two clock cycles; release reset cleanly. The cited minimum is a W65C02S specification, not a universal rule for every 6502-family processor. Consult the selected CPU datasheet for its electrical requirements.
- Check CPU-to-ROM fetches before adding peripherals. Program a small, known ROM image with a reset vector pointing to its intended entry point. After reset, check that the CPU accesses the expected ROM addresses. Leave LCDs, UARTs, and other peripherals disconnected until this basic fetch works.
- Add SRAM and test it. Try reads and writes at representative mapped addresses, including low-page and stack-region locations. Check for swapped address or data lines, unintended mirroring, and overlapping selects. Choose test addresses to expose the aliases your map could create; this is a recommended procedure, not a reported test result.
- Add one input/output path. A VIA can provide parallel I/O, while an ACIA or another serial solution can provide terminal interaction. Select one expansion and verify its address decoding after the memory core works. Documented projects demonstrate both serial and LCD/VIA expansions; see the Mike 42 65C02 computer and HB6502 project.
Diagnose common first-start problems
- No meaningful address activity after reset: Check power and ground, PHI2, RESB polarity and timing, BE state, and whether the bytes at $FFFC/$FFFD point into ROM that is actually mapped there.
- Repeated or mirrored addresses: Check continuity on A0–A15, the memory-capacity assumptions in your map, decoder inputs, and any upper address bits the decoder ignores. Ignored bits can make multiple CPU addresses select the same physical memory location.
- Bad or unstable reads: Verify that only one device drives D0–D7 on a read, RWB is connected and interpreted correctly, ROM is enabled at the reset vector, and all devices meet the bus timing at the selected clock rate.
- Writes do not persist: Confirm the SRAM select and write-enable signals assert only for intended writes. EEPROM is not a drop-in substitute for SRAM’s ordinary writable working memory.
- Execution begins at the wrong address: Check the ROM image offset, map boundaries, and low-byte/high-byte order in the reset vector. The Crab Apple guide explicitly calls for an image covering $E000–$FFFF.
Choose trade-offs deliberately
A simple decoder can reduce logic complexity but may leave address space unused or tie the design to a particular map. A PLD can make more flexible decoding possible, at the cost of adding a programmable part and its configuration step. Likewise, a fixed oscillator is straightforward once the design is stable, while an adjustable clock can make slow, observable bring-up easier. Published examples span roughly 1 MHz to 1.8432 MHz, but those are project choices, not safe universal targets; the permissible rate depends on the timing specifications of the exact CPU and every attached device.
For a first visible milestone, choose either a simple LED/parallel-output test or a serial terminal path rather than building several peripherals at once. The important design choice is to add only one new bus device at a time, so a new failure has a small set of likely causes.
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