A delta-sigma fractional-N synthesizer lets a phase-locked loop (PLL) tune in fine frequency steps by rapidly varying its divider ratio and shaping the resulting quantization noise. For software-defined radio (SDR), that can make it practical to retune across channels with one synthesizer instead of relying on a separate fixed-frequency source for each channel. The trade-off is that range, hop time, phase noise, spurs, power and reference-clock limits have to be designed together.
How a fractional-N PLL creates fine frequency steps
A PLL compares a divided-down version of its output with a reference clock, then adjusts a voltage-controlled oscillator (VCO) to keep them aligned. In an integer-N PLL, the divider uses a whole-number ratio, so the output frequency is tied to integer multiples of the phase-detector frequency. That can make small frequency steps difficult unless the reference or phase-detector frequency is also made small.
A fractional-N PLL makes the average divider ratio fractional. For example, it can alternate among nearby integer divider values so that, over time, the average division ratio includes a fractional part. This allows output-frequency steps smaller than the reference frequency while keeping the phase-detector frequency relatively high.
What the delta-sigma modulator adds
The divider cannot divide by a fraction on any one cycle, so the modulator chooses a sequence of integer values whose average is the desired fractional ratio. A delta-sigma modulator shapes the sequence’s quantization noise, moving much of its energy toward higher offset frequencies. The PLL loop filter attenuates part of that out-of-band energy. TI describes this combination in the LMX2470 as pushing lower-frequency fractional spurs to higher frequencies outside the loop bandwidth.
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Noise shaping does not mean that fractional spurs or phase noise disappear. Their behavior depends on the modulator, reference, divider settings, loop filter and operating point; spur and phase-noise performance must be checked at the offsets that matter to the radio.
Why this matters for software-defined radio
An SDR can command a synthesizer to move its local-oscillator frequency as the software changes channel or operating mode. Fractional tuning makes small channel spacings possible without requiring a separate crystal for every channel. It can therefore support frequency agility with a compact RF source, but does not by itself provide a complete transceiver: mixers, filters, amplifiers, converters, control logic and antenna-path switching may still be needed.
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- NESDR SMArt RTL-SDR v5 can be used for the reception of broadcast AM radio, broadcast FM radio, shortwave radio, CB radio, public security radio, trunked radio, air traffic control, ACARS (plane-ground communications), ADS-B (plane tracking), AIS (ship tracking), POCSAG (pagers), NOAA and GOES weather satellites (weather images), weather balloons, radiosondes, DAB radio, DVB-T video, Inmarsat, Iridium, and so much more!
- The best-performing low-cost RTL-SDR available anywhere! Compared with RTL-SDR v3, HF SNR is improved by up to 15dB, VHF & UHF SNR is improved by up to 6dB, tuning accuracy is improved by an average of 4x, and the frequency range is expanded all the way down to 100kHz
- v5 has a frequency capability of 100kHz to 1.75GHz and up to 3.2MHz of instantaneous bandwidth. HF reception below 25MHz is accomplished with direct sampling and requires a suitable antenna. We recommend using a Balun One Nine to make a DIY long wire or dipole antenna (sold separately, product ID B08HGSYB7R or B00R09WHT6)
- Though the direct sampling implementation of NESDR SMArt v5 is much better than any other RTL-SDR, we still recommend using an upconverter like the Ham It Up for a more fulfilling HF experience (sold separately, product ID B076CYK8XZ)
“Frequency-agile” also does not automatically mean instantaneous hopping. A new frequency must be programmed, the PLL must settle, and the surrounding RF chain may need time to switch or stabilize. FastLock features can help under specified conditions, but the actual usable hop time is system-specific.
What the published low-power result establishes
A 2019 peer-reviewed design by Zhang and coauthors in IET Circuits, Devices & Systems reports a 65 nm CMOS wideband synthesizer for SDR, operating from a 1.2 V supply. The publication reports measured 0.1–5 GHz output coverage and maximum power consumption of 21 mW in regular mode and 10.2 mW in low-power mode. It reports phase noise of −120.3 dBc/Hz at a 1 MHz offset at 2.75375 GHz in regular mode, and −122.8 dBc/Hz at a 1 MHz offset at 1.3525 GHz in low-power mode.
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These are results for that specific published design and its stated modes and measurement points—not general guarantees for fractional-N synthesizers, nor specifications for the commercial parts below. In particular, the phase-noise figures are at different carrier frequencies and modes, so they are not a direct same-condition comparison.
Commercial synthesizers and a prototype board to consider
The examples below illustrate different design priorities. The ranges and typical-current figures are vendor-stated specifications summarized here; they should not be treated as a substitute for checking the full datasheet and conditions for a particular design.
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| Device or board | Documented range or coverage | Relevant features | Power or hop-time information |
|---|---|---|---|
| TI LMX2470 | 500 MHz–2.6 GHz RF PLL | Selectable 12- or 22-bit fractional modulus; programmable delta-sigma modulation up to fourth order; fastlock, cycle-slip reduction and hardware/software power-down. | TI lists typical current of about 4.1 mA. A specific hop-time figure is not stated here. |
| TI LMX2486 | 1–4.5 GHz RF PLL | Selectable 12- or 22-bit fractional modulus; delta-sigma modulation up to fourth order; phase-detector frequency up to 50 MHz. | TI lists typical current of about 5.7 mA. A specific hop-time figure is not stated here. |
| TI LMX2571 | 10 MHz–1344 MHz continuous output, using integrated VCO cores and output dividers | Supports direct digital FSK and TI’s FastLock technique. | TI says frequencies can be stepped in less than 1.5 ms under its specified conditions; this is not a universal system hop-time guarantee. Typical current is not stated here. |
| Analog Devices ADF4356 evaluation board | Board-level output coverage is not stated here. | Documents an ADF4356 fractional-N/integer-N synthesizer platform. The evaluation board includes a 122.88 MHz reference, loop filter, USB interface, regulators and SMA connectors. | Board or IC power and hop-time figures are not stated here. |
When the LMX2470 or LMX2486 fits
The LMX2470 is a useful candidate to investigate when its 500 MHz–2.6 GHz range covers the target and low typical current is important. The LMX2486 extends the documented range to 4.5 GHz and supports a phase-detector frequency up to 50 MHz, with a higher listed typical current. Neither range alone establishes performance at every frequency: check the datasheet for reference and divider constraints, output behavior, phase noise, spurs and required external circuitry.
When the LMX2571 fits
The LMX2571 is relevant when modulation and channel changes matter alongside output coverage. Its integrated VCO cores and dividers provide a continuous 10 MHz–1344 MHz output range, and its direct digital FSK support may suit applications that need frequency modulation. Treat the less-than-1.5-ms FastLock statement as a vendor claim under specified conditions; the available summary does not define those conditions, so validate timing for the intended configuration.
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What the ADF4356 evaluation board provides
The ADF4356 board offers a practical RF synthesizer bring-up platform: a reference, loop filter, USB interface, regulators and SMA connectors are included. It can help evaluate the synthesizer path before committing to a custom board, but it is not a complete SDR transceiver. Confirm the board’s frequency coverage, software support and compatibility with the rest of the intended RF chain from its documentation before selecting it.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to choose and validate a synthesizer for an SDR
- Start with the channel plan. Write down the lowest and highest local-oscillator frequencies, channel spacing, required tuning step, modulation modes and whether tuning must be continuous across the band. A chip’s headline frequency range does not establish that every frequency and step is supported in the same configuration.
- Choose the reference and phase-detector rate together. The reference frequency, reference divider and phase-detector frequency affect achievable tuning resolution and loop design. Check the device’s supported reference and PFD limits before assuming a desired step size is available.
- Define the hop-time requirement. Measure from the software’s frequency-change command to when the RF output is stable enough for the receiver or transmitter to use. Include programming, PLL settling and any RF switching or calibration; do not equate a FastLock feature with end-to-end SDR retuning time.
- Design the loop bandwidth around competing needs. A wider loop can help settling and suppress more close-in reference-related noise, while loop bandwidth also affects how shaped fractional noise and spurs pass through. Use the vendor’s simulation tools with the actual reference, VCO and loop-filter components rather than choosing bandwidth from a generic rule.
- Check spectral behavior at relevant offsets. Review phase noise at offsets that affect the wanted signal and adjacent channels, and inspect fractional spurs, reference feedthrough and integer-boundary behavior across the tuning range. A single phase-noise number at one offset is not a full spectral-performance description.
- Check electrical and RF limits over operating conditions. Verify VCO tuning range, divider limits, supply and current requirements, output level, temperature behavior and the reference source’s quality. Confirm that the chosen part’s implementation requirements match the intended board and power budget.
- Prototype before committing to a custom PCB. Use an evaluation board and configuration or simulation tools to establish a stable loop and test the planned channel changes. Then validate the complete RF path on the intended hardware, because a synthesizer-only result does not capture every system-level settling or interference effect.
Cost and power are design outcomes, not automatic properties
Fractional-N tuning can reduce the need for many fixed-frequency references and can make a single programmable source cover multiple channels. That can simplify an SDR architecture, but it does not establish that a finished radio will cost less: board components, filtering, shielding, control circuitry, manufacturing and performance requirements all affect the result. Likewise, a low-power mode or a chip’s typical-current figure does not establish total radio consumption; compare measurements and specifications under matching supply, frequency, output and operating-mode conditions.
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