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Gen-Z PHY Specification 1.1 added PCIe Gen 5 support to its PCIe physical-layer clause and introduced separate 50G PAM4 clauses for Fabric and Local links. The specification is a technical standard for physical-layer behavior—not a product announcement, and not evidence that every PCIe Gen 5 product implements Gen-Z.

What changed in Gen-Z PHY Specification 1.1?

The revision change summary lists three updates: the existing Gen-Z-E-NRZ-PCIe clause was enhanced to support PCIe Gen 5, and two clauses were added: Gen-Z-E-PAM4-50G-Fabric and Gen-Z-E-PAM4-50G-Local. These are distinct physical-layer options, not interchangeable names for a single 50G interface. The 2019 announcement describes PCIe Gen 5 signaling at 32 GT/s per lane, compared with Gen 4 at 16 GT/s per lane. GT/s is a signaling rate; it does not by itself specify application data throughput.

What does a PHY specification define?

A PHY, or physical layer, specifies how devices communicate across a physical medium. The Gen-Z specification describes its scope as “logical, functional, electrical, and channel characteristics” for physical layers that connect Gen-Z core layers to other devices through particular media and signaling interfaces. It is organized into clauses so that physical-layer variants for different applications can be developed in separate cycles.

In practice, this is an engineering document with detailed signaling, electrical, and channel requirements. Its appendix includes example insertion-loss budgets for specified Gen-Z PCIe 32G add-in-card configurations and Gen-Z 50G Fabric and Local add-in-card configurations. Those examples are tied to the document’s configurations and test assumptions; they should not be treated as universal limits for every card, link, or reach.

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UGREEN PCIe Ethernet Card 5G, for Windows 11/10, Linux Kernel 5.17 or Newer
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What does “50G PAM4” mean here?

The announcement describes Gen-Z 50G as using four-level pulse amplitude modulation (PAM4) and low-latency forward error correction (FEC) to support link reliability. PAM4 encodes information using four signal levels. FEC adds error-correction information so a receiver can detect and correct some transmission errors. The Fabric and Local clauses specify separate PHY cases; the exact requirements and channel constraints for a particular implementation must be taken from the relevant clause in the specification.

When was revision 1.1 published?

The PDF’s revision change summary dates version 1.1 to September 17, 2019. The public announcement that the specification was available for download followed on September 30, 2019. These dates refer to the document revision and its announcement, respectively. The CXL-hosted Gen-Z Specification Archive, dated February 16, 2024, lists PHY Specification 1.1 for download.

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How does this relate to PCIe today?

Gen-Z PHY 1.1’s PCIe Gen 5 support was an addition in the 2019 revision, not a claim that Gen 5 is PCIe’s newest capability. As checked September 27, 2026, PCI-SIG lists PCI Express Base Specification Revision 7.1, dated September 17, 2026, as the current approved base revision; PCIe Base 5.0 is listed with a date of May 28, 2019. See PCI-SIG’s PCI Express Base page for its current status listing.

The distinction matters for compatibility: support for PCIe Gen 5 in a Gen-Z physical-layer clause does not make every PCIe Gen 5 device, card, or link a Gen-Z implementation. A product’s actual supported standards and PHY configuration must be established from its own documentation.

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