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For a first hands-on XMOS project, start with the XMOS XK-EVK-XU316 xcore.ai Evaluation Kit. Its two-tile XU316 processor has 16 logical cores in total, and the board brings audio, USB, camera, GPIO and debug connections together so you can explore concurrent real-time work without first designing a carrier board.
The useful difference from a conventional MCU is not simply the core count: xCORE devices are built to run concurrent tasks and handle communication and I/O with hardware support. That makes them worth exploring when several timing-sensitive jobs—such as audio capture, signal processing and control—need to proceed predictably alongside one another.
What an XMOS multi-core MCU is—and what “deterministic” means
XMOS xCORE devices use a tiled multicore architecture. A tile contains multiple logical processors that share program and data memory. The cacheless design is intended to make execution timing more predictable than systems where cache behavior can add variability. XMOS’s XS2 architecture also provides direct support for concurrent processing, inter-processor communication and I/O; xConnect links support communication in multi-chip systems.
“Deterministic” should be understood as an architectural aim, not a blanket guarantee that every application has fixed timing. Your code, task partitioning, I/O configuration and interactions still matter. A useful experiment is to measure a timing-sensitive signal while other tasks run, rather than assume that the chip’s architecture alone proves your application’s timing.
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The xcore.ai family combines programmable I/O, control processing, DSP and AI capabilities. XMOS advertises software-defined I/O and nanosecond timing, and lists up to 3200 MIPS for 800 MHz package options on its xcore.ai product page. That figure applies to those package options; it should not be treated as the performance of every XMOS device or the XK-EVK-XU316 board in every workload.
Which XMOS board should you use first?
Start with the XK-EVK-XU316 evaluation kit
XMOS positions the XK-EVK-XU316 as a general software-development board for evaluating xcore.ai and running simple tests and demos. Its processor is the XU316-1024-FB265, a two-tile device. Each tile is user-programmable and provides eight logical cores, for 16 logical cores across the chip.
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| Kit detail | What XMOS specifies |
|---|---|
| Processor | XU316-1024-FB265; two tiles, with eight logical cores per tile and 16 total (XMOS XK-EVK-XU316 hardware manual, revision 2.0). |
| Compute figures | Up to 1400 MIPS/MFLOPS and 40 GMACC/s vector performance, as stated by XMOS for the kit in hardware-manual revision 2.0. These are published peak figures, not a measured result for a particular application. |
| Digital I/O | 58 general-purpose digital I/Os, as stated in the XMOS hardware manual, revision 2.0. |
| Memory and audio | QSPI flash, optional LPDDR1 external memory, an audio codec with line-in and line-out, and a PDM microphone connector. |
| Other connections and controls | USB for power/host, MIPI camera connectivity, GPIO headers, LEDs, push buttons and an XSYS2 debug connector. |
| Price and availability | XMOS’s kit page showed a price from $140 when crawled; current price and stock can vary. XMOS lists Digi-Key, Mouser, WPG Americas and Astute Electronics as distributor channels. |
The interface mix is useful for experiments in audio, camera input, USB, GPIO timing and control without building a custom board first. Check current kit documentation and distributor listings for what is included, regional availability and the board revision before ordering.
When a different board may make more sense
If your goal is specifically to evaluate xcore.ai software with several real-world interfaces attached, this kit is a practical fit. If you already have a design with fixed connector, memory or peripheral requirements, compare those against the kit before choosing it: an evaluation board’s convenience does not guarantee that its connections match a finished product.
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How to get a first program running
XMOS’s programming guide says example applications require XTC Tools 15.2.1 or newer and CMake 3.21 or newer. Tool releases change, so use the current XMOS instructions for installation and host compatibility rather than relying on an old setup tutorial.
- Install the development tools. Install a current XTC Tools release and CMake 3.21 or newer. Confirm the installed tool versions against the requirements for the particular example you intend to build.
- Connect the board for development. Use the board’s debug connection and follow the applicable XMOS example instructions for USB/JTAG access. The kit also has USB for power/host; do not assume every USB connection serves the same purpose.
- Build and run a supplied board example. Begin with an example intended for the XK-EVK-XU316. This checks the basic toolchain, board connection and build configuration before you introduce application-specific code.
- Split work by function. Keep independent jobs—such as input capture, processing and output—in separate logical cores or threads where appropriate. Use the architecture’s channels and links to communicate between tasks, rather than treating the logical cores as unrelated single-core MCUs.
- Add one timing-sensitive I/O task. Generate or capture a signal, then observe its behavior while other DSP or control work is running. Change one variable at a time so you can see how the application’s partitioning and workload affect timing.
- Move to libraries or an RTOS when useful. Once the bare-metal concurrency model is clear, explore XMOS libraries for relevant functions or multicore FreeRTOS support if your application benefits from that environment.
Experiments that show what the architecture is good at
Measure deterministic I/O under load
Use GPIO or a serial/custom protocol task to generate or capture precisely timed events. Run another workload at the same time and compare the observed timing. This tests the property that matters in practice—whether your complete design maintains the timing it needs while doing other work.
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Build an audio capture and processing path
The board’s PDM microphone connector and audio codec give you ways to explore capture and playback. XMOS’s xcore.ai DSP overview lists PDM interfaces, acoustic echo cancellation, noise suppression, asynchronous sample-rate conversion and automatic gain control. A manageable project is to partition capture, filtering and transport across tasks, then add processing stages as you understand the data flow.
Try a voice-interface pipeline
Combine microphone input with codec line-in/line-out as appropriate for the design, and keep capture, filtering and transport as separately understandable jobs. This is a useful way to explore the relationship between real-time I/O and DSP without beginning with an AI model or a complex finished product.
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Explore small edge-AI workloads
The xcore.ai vector unit and software flow are intended to support AI as well as DSP and control. Try a small inference workload while reserving other tasks for I/O and control. Keep the scope to the model and data path your chosen software flow supports; the product-family headline MIPS figure is not a prediction of a particular model’s performance.
Prototype sensor or motor control
Programmable I/O and concurrent scheduling are relevant when a control loop has to respond repeatably while other functions run. A bench experiment can start with a sensor input and a GPIO output before connecting more consequential hardware. Validate electrical levels, timing and safety requirements for the actual peripherals you use.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How XMOS differs from a conventional single-core MCU
A single-core MCU may be the simpler choice when the workload is modest, the peripheral set is conventional and one control loop can meet timing needs. XMOS is most compelling when an application benefits from multiple concurrent real-time functions and flexible I/O. Compare the design along these dimensions:
Quick Recap
| Decision area | What to examine |
|---|---|
| Timing and concurrency | Does the application need several real-time tasks to run concurrently with predictable timing, or can one core schedule them adequately? |
| Core organization | Does the tile-and-logical-core model fit how you want to partition tasks? For the XU316-1024-FB265 on this kit, the documented arrangement is two tiles with eight logical cores each. |
| Custom I/O | Will programmable I/O simplify an interface that would otherwise require extra logic or a different peripheral arrangement? |
| DSP and AI software | Do XMOS libraries and the xcore.ai software flow cover the processing functions you need? Check the specific library and example requirements before basing a design on them. |
| Memory and peripherals | Does the board or target device provide the memory, audio, camera, USB and GPIO facilities the application requires? |
| Development effort | Are you prepared to learn tile memory, channels, task scheduling and the XTC toolchain? A familiar single-core workflow may be easier if the extra concurrency is not valuable to the project. |
What to learn before scaling up
- Tile memory: Understand how code and data are organized and shared within the tile model before assigning work across cores.
- Communication: Learn how channels and links support communication between concurrent tasks, and design the data exchange as deliberately as the tasks themselves.
- Scheduling and timing: Define what must happen on time, then measure it while representative concurrent workloads are active.
- Toolchain and libraries: Match examples and libraries to the XTC Tools version you install; do not assume an older guide’s setup or compatibility remains current.
- Hardware fit: Check the needed memory and peripherals against the board and eventual target, especially before moving from a demo to a product design.
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