Design the tree from the SoC vendor’s rail table, not from a favorite PMIC. Separate the hundreds-of-ampere core rails from lower-power system rails, protect every converter against the vehicle battery’s worst transient, then add sequencing, supervision, diagnostics and thermal/EMC validation. Monolithic Power Systems (MPS) covers this partition with digital multiphase controllers, monolithic DrMOS stages, ASIL-oriented PMICs and dedicated safety monitors.
1. Start with the SoC rail table
Before selecting an MPS device, obtain the target SoC vendor’s complete power specification. Record each rail’s nominal voltage, tolerance, maximum steady-state and transient current, allowed ramp rate, sequencing dependency, power-good behavior and any dynamic-voltage or frequency-scaling range. Also capture whether the SoC requires remote sensing, a minimum slew rate, a particular switching-frequency range or a defined response to an overvoltage, undervoltage or missing-clock fault.
Separate core power from system power
MPS describes automotive SoC core rails as potentially requiring hundreds of amperes, with demanding transient and efficiency requirements. Memory, I/O, sensor, transceiver and housekeeping rails normally draw much less current and can be supplied by PMIC channels or individual point-of-load converters. Treat the core path as the first sizing exercise: its current, phase count, inductors, output capacitors, bus bars and heat-spreading strategy influence the rest of the board.
Illustrative rail set
The following values come from an MPS worked power-tree example published approximately in 2022; they are an example, not a specification for every SoC.
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| Rail | Example voltage | Example current | Design implication |
|---|---|---|---|
| SoC core | 0.85 V | 60 A | Use a multiphase converter with remote sensing, carefully selected inductors and substantial low-ESR output capacitance. |
| System rail | 1.8 V | 5 A | A medium-current buck or PMIC channel may be suitable after checking transient demand. |
| I/O rail | 3.3 V | 5 A | Check peripheral startup loads and noise limits, not only average current. |
| Auxiliary rail | 1.05 V | 6 A | Verify the SoC’s tolerance and sequencing relationship to the core rail. |
| Auxiliary rail | 0.6 V | 6 A | Low voltage leaves little margin for IR drop and sensing error. |
2. Choose the battery-input architecture
The battery transient determines whether the high-current stage can connect directly to the vehicle supply. MPS describes up to 20 V for lithium-ion 12 V systems and up to 40 V transient voltage for lead-acid systems. Compare the converter’s absolute maximum rating, recommended operating range and transient duration with the vehicle-level requirement; a nominal “12 V” label is not sufficient.
| Approach | When it fits | Advantages | Costs and risks |
|---|---|---|---|
| Direct, single-stage conversion | The input transient remains inside the power stage’s validated rating. MPS gives a 22 V-rated DrMOS as an example that can support a stated 20 V lithium-ion maximum. | Fewer conversion stages, lower component count and potentially higher efficiency. | Little voltage margin; input protection, layout and thermal validation become critical. |
| Pre-regulator before the core converter | Lead-acid load-dump or double-battery conditions can exceed the DrMOS rating. A pre-regulator can limit the downstream input to about 20 V. | Protects the high-current stage while preserving a high-current downstream architecture. | Adds switching loss, control interaction, magnetics and another fault path. |
| Two-stage intermediate bus | Create a 5 V or 3.3 V bus, then use a low-voltage DrMOS rated around 6 V for the SoC rails. | Enables compact low-voltage power stages and predictable downstream conditions. | Two conversion stages reduce end-to-end efficiency and require coordinated startup and fault handling. |
Include reverse-battery protection, cold-crank behavior, load-dump clamping, input filtering and conducted/radiated-emissions targets in the same architecture decision. Do not select a pre-regulator solely from its nominal current; check its transient response and interaction with the downstream control loops.
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3. Size the high-current SoC rail
Set phase count from current and transients
Use the SoC’s maximum and step current, allowable voltage excursion and switching frequency to determine the number of phases. More phases distribute conduction and switching loss, reduce per-phase inductor current and can improve transient response, but they add inductors, layout area and current-sharing verification. The phase count must also fit the controller’s configuration and the selected DrMOS thermal envelope.
Use a monolithic DrMOS stage
MPS describes its DrMOS as integrating the gate-driver IC, current-sensing circuit and temperature-sensing circuit. This removes several external components used by traditional discrete MOSFET solutions and provides a compact, repeatable phase design. Confirm the stage’s input-voltage rating, continuous and peak current, current-sense method, switching frequency, dead-time behavior and thermal derating at the intended copper area and airflow.
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Control current sharing and sensing
Place each inductor and DrMOS symmetrically, keep high-current loops short and use the controller’s recommended Kelvin or remote-sense connections. Validate phase-current balance across line, load, temperature and manufacturing tolerances. Sense at the SoC load, while separately checking connector, plane and via IR drop; a regulator can regulate its sense point accurately while the silicon still sees an excessive drop.
4. Select an MPS controller and power stages
MPQ2977-AEC1 for multiphase core conversion
MPS describes the MPQ2977-AEC1 as a digital controller configurable for two rails with three phases per rail. It includes overcurrent, overvoltage and overtemperature protection. Pair it with a DrMOS whose voltage and current ratings match the battery architecture and the calculated phase stress. The controller’s available phase combinations are a starting point, not proof that a given SoC rail is covered; check the SoC transient profile and thermal model first.
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DrMOS selection checks
- Input-transient rating with the required margin, including the chosen pre-regulator’s worst-case overshoot.
- Peak and thermal current at the actual switching frequency, inductance, duty cycle and PCB copper.
- Current-sense accuracy and temperature-reporting behavior over production tolerance.
- Compatibility with the controller’s gate-drive timing, fault thresholds and enable sequence.
- AEC-Q100 grade, package derating and the board’s heat-spreading capability.
5. Supply lower-power rails with a safety-oriented PMIC
For 5 V intermediate buses and lower-current ADAS rails, MPS positions the MPQ70160FS-AEC1 as an ASIL-D PMIC. Its six buck outputs are described as two 4 A channels, two 3 A channels and two 1 A channels. Map those ratings against each rail’s peak, startup and transient current rather than assigning channels by average consumption. Check dropout, switching-frequency interaction, output-noise limits and whether channels can be paralleled or must remain independent.
Keep sensitive analog, memory and transceiver supplies on the channel whose voltage accuracy, noise and sequencing behavior meet that device’s requirements. If a rail exceeds the PMIC channel rating or has an unusually fast load step, use a dedicated point-of-load converter and supervise it with the safety monitor.
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6. Add sequencing, monitoring and fault response
Voltage supervision with MPQ79500FS-AEC1
MPS describes the MPQ79500FS-AEC1 as providing six-channel undervoltage/overvoltage supervision, remote sensing, timestamp capture, I2C access and built-in self-test (BIST). Allocate channels to the rails whose failure can damage the SoC or violate the safety goal, and define thresholds, debounce times, timestamp use and the reaction to each fault. Confirm that six channels cover the rails that must be monitored independently; additional rails may need another monitor or a grouped diagnostic justified by the safety analysis.
Sequencing with MPQ79700FS-AEC1
The MPQ79700FS-AEC1 is described by MPS as a 12-channel functional-safety power sequencer for ADAS and autonomous-driving platforms. It provides 12 enable outputs, time-slot sequencing, watchdog, reset and interrupt functions, I2C with CRC, OTP configuration and BIST. Program dependencies so that downstream rails cannot enable before their prerequisites are valid, and specify what happens on a brownout, watchdog timeout, communication error or failed BIST.
Functional-safety boundary
MPS describes its MPSafe process as ISO 26262 compliant and supporting products up to ASIL-D. That product capability does not complete the vehicle’s safety case. The system designer must allocate safety goals, calculate diagnostic coverage and hardware metrics, define safe-state and fault-reaction timing, control software configuration, and provide the evidence required for the chosen ASIL. Include the SoC vendor’s assumptions and dependent-failure analysis.
7. Use the EVME6L_00A design as a topology reference
MPS’s EVME6L_00A reference design for Mobileye EyeQ6L, documented in 2024, contains nine output rails, 12 monitored voltage rails, 12 sequencer channels and a pre-regulator rated up to 20 A. Use those figures to check whether your proposed architecture has enough conversion, monitoring and sequencing capacity. It is a topology checklist, not a drop-in schematic: EyeQ6L rail voltages, current transients, startup dependencies, battery profile and safety assumptions may differ from another SoC.
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8. Close EMC, thermal and vehicle-level validation
A power tree that regulates correctly on the bench can still fail vehicle qualification. Plan validation around the complete operating envelope.
Quick Recap
- Input conditions: cold crank, engine restart, load dump, double-battery exposure, reverse battery and conducted transients for the target battery chemistry.
- Power integrity: line and load regulation, fast current steps, startup overshoot, phase-current sharing, remote-sense accuracy and SoC-side voltage at the worst IR drop.
- Thermal: DrMOS and inductor temperature at maximum ambient, maximum duty cycle and sustained SoC load, including enclosure and airflow limits.
- EMC: switching-frequency selection, phase staggering, input/output filtering, return-current control, spread-spectrum options and CISPR25 conducted and radiated tests.
- Safety: threshold accuracy, watchdog timing, reset pulse width, fault injection, BIST behavior, I2C/CRC error handling and diagnostic coverage.
- Production: OTP or nonvolatile configuration controls, programming access, component tolerances, end-of-line tests and evaluation-board correlation.
9. A practical selection sequence
- Freeze the SoC rail table, including maximum transient current and sequencing dependencies.
- Partition rails into high-current core paths and lower-power PMIC or point-of-load paths.
- Derive the battery worst case from the vehicle requirements, distinguishing lithium-ion 12 V limits from lead-acid transients.
- Choose direct conversion, a pre-regulator or a 5 V/3.3 V intermediate bus based on validated voltage margins.
- Size phase count, inductors, DrMOS ratings, output capacitance and thermal paths for the core rail.
- Map remaining rails to PMIC channels such as the MPQ70160FS-AEC1, checking peak and startup current.
- Assign supervision and sequencing channels using devices such as MPQ79500FS-AEC1 and MPQ79700FS-AEC1.
- Document watchdog, reset, interrupt and fault-reaction behavior, then update the ISO 26262 safety case.
- Validate regulation, transients, thermal performance, EMC and vehicle input events before releasing the layout.
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