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Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Peking University researchers reported a wafer-scale, silicon-free 2D transistor system in a Nature Materials paper published on 14 February 2025. The study reports a 30 nm gate-length device with a 1.9 ps intrinsic delay, but those are transistor-level research results—not evidence that a commercial processor is faster than today’s silicon CPUs.
What the researchers built
The team integrated a two-dimensional semiconductor, Bi2O2Se, with a layered native-oxide high-κ dielectric, Bi2SeO5, in a gate-all-around (GAA) structure. The reported approach uses low-temperature, monolithic three-dimensional integration to create wafer-scale, multilayer-stacked structures of single-crystalline 2D materials. The Nature Materials paper describes the device architecture and measurements.
In a GAA transistor, the gate surrounds the channel, giving it control from multiple sides. That can improve electrostatic control as devices are scaled. “Silicon-free” here is shorthand for the active 2D semiconductor and dielectric reported in this device; it does not mean silicon has been removed from chip manufacturing or the broader supply chain.
What the reported measurements show
The paper reports material and device metrics, including electron mobility of 280 cm² V⁻¹ s⁻¹ and a subthreshold swing of 62 mV/dec. Subthreshold swing describes how much gate voltage is needed to change a transistor’s current by a factor of ten; a lower value indicates sharper switching. For a scaled device with a 30 nm gate length, the study reports the following:
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| Metric | Reported result |
|---|---|
| Gate length | 30 nm |
| Operating voltage | 0.5 V |
| On-state current | Greater than 1 mA/μm |
| Intrinsic delay | 1.9 ps |
| Energy-delay product | 1.84 × 10⁻²⁷ J s μm⁻¹ |
These are device-level figures reported in the study, not benchmark results for a complete processor. A transistor’s intrinsic delay does not by itself predict how quickly a CPU executes programs: processor performance also depends on circuit design, interconnects, memory, power limits, and many other factors. The 30 nm figure is the device’s gate length, not a “30 nm chip node.”
Is it faster or more efficient than silicon chips?
The research team was reported as claiming that its transistor could operate up to 40% faster while using 10% less energy than advanced 3 nm silicon chips. The South China Morning Post’s account attributes that comparison to the team. It should not be read as an independently verified, apples-to-apples result showing that a finished chip built with this technology outperforms commercial processors.
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Tom’s Hardware reported the group’s wafer-scale claim and quoted team leader Professor Hailin Peng describing the device as “the fastest, most efficient transistor ever.” That is an attributed superlative, not an established all-time ranking across transistor designs and measurement conditions. Tom’s Hardware’s report provides that context.
Is the transistor available in products?
No consumer product or commercial launch date is established by the cited reports. This is a research demonstration, not a retail processor or a replacement for silicon chips in devices. The paper discusses future prospects for beyond-silicon monolithic 3D circuits, which describes a research direction rather than current deployment.
Scale-up is also a broader challenge for 2D transistors. Nanjing University’s overview of the field identifies reliable, cost-effective, large-scale manufacturing as an outstanding hurdle; that is field context, not a direct assessment of this team’s production yield or process. Nanjing University’s overview discusses the wider manufacturing challenge.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why the result matters—and what it does not prove
The work is notable for combining a 2D channel and its layered native-oxide dielectric in a wafer-scale stacked GAA research structure, alongside promising device metrics. It offers a possible path for studying future transistor and circuit designs beyond conventional silicon-based architectures. It does not yet establish manufacturing yield, long-term reliability in products, commercial economics, or a timetable for adoption.
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Peng summed up the research direction to the South China Morning Post with a metaphor: “If chip innovations based on existing materials are considered a ‘short cut’, then our development of 2D material-based transistors is akin to ‘changing lanes’.” The quotation captures the team’s ambition; it is not evidence that the technology is ready for commercial use.
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