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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteCEA-Leti, CEA-List and Powerchip Semiconductor Manufacturing Corporation (PSMC) announced a collaboration on 3 April 2026 to combine customizable RISC-V processors, silicon-photonic short-reach links and 3D-stacking/interposer platforms for next-generation AI systems. The announcement describes intended development and foundry services—not a disclosed prototype, benchmark or commercial product.
What the collaboration combines
The partnership brings together three capabilities:
| Organisation | Contribution named in the announcement |
|---|---|
| CEA-List | RISC-V processor and design expertise |
| CEA-Leti | Silicon-photonics expertise, including microLED-based optical communication research |
| PSMC | Established 3D-stacking and interposer platforms, plus planned foundry services |
The intended system architecture pairs flexible RISC-V compute with optical links that move data between closely integrated chips or chiplets. PSMC’s packaging platforms are intended to provide the physical integration layer.
How RISC-V fits the proposed AI systems
RISC-V is an open instruction-set architecture that can be customized for particular products. CEA-List Deputy Head Olivier Thomas said its openness, flexibility and cost efficiency allow industrial users to tailor processors to their needs. In this project, that flexibility is presented as a way to build application-specific compute alongside advanced packaging rather than relying only on fixed, general-purpose processor designs.
The Tool Desk
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
The release does not identify a processor model, core count, accelerator design, manufacturing process, operating frequency or completed chip. Those implementation details remain undisclosed.
Why add silicon photonics to 3D stacking?
Traditional copper connections become harder to scale as systems move more data across tightly packed components. The partners frame short-reach optical communication as a possible way to address bandwidth demand and power constraints in AI hardware. Optical links would carry data between nearby components, while 3D stacking and interposers provide dense physical connections among those components.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
CEA-Leti CEO Sébastien Dauvé described microLED as a critical enabling technology for increasing optical-communication throughput with low-power gallium-nitride (GaN) LED solutions. The announcement does not specify the optical wavelength, link distance, modulation method, bandwidth, energy per bit, coupling structure or packaging process.
What PSMC says it plans to offer
PSMC says the collaboration will expand its 3D-stacking and interposer technology envelope with RISC-V computing IP and high-bandwidth silicon-photonics chiplet communication. It also says the partners intend to provide foundry services for customers developing next-generation AI applications.
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Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
That statement describes a planned service direction. No customer list, product catalog, order process, pricing, manufacturing volume, qualification status or launch date has been announced.
What is—and is not—established
| Question | Status from the 3 April 2026 announcement |
|---|---|
| Has a collaboration been announced? | Yes. CEA-Leti, CEA-List and PSMC announced it on 3 April 2026. |
| Are the technology areas identified? | Yes: customizable RISC-V compute, silicon-photonic short-reach links, microLED/GaN optical technology, and 3D-stacking/interposer platforms. |
| Is measured performance available? | No numerical bandwidth, latency, energy, compute, yield or efficiency results are provided. |
| Is a prototype confirmed? | Not stated. |
| Are process and architecture details available? | Not stated. |
| Are commercial timing and terms available? | Not stated. |
How the approach should be evaluated when results appear
Future technical disclosures would need to show more than the presence of optical links or 3D packaging. Useful comparison measures include:
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
- Optical-link bandwidth: aggregate and per-link data rates under defined conditions.
- Energy per bit: transmitter, receiver and packaging overhead, rather than an optical component alone.
- Reach and latency: the distance supported inside the package and the end-to-end communication delay.
- Integration density: chiplet count, interconnect pitch, stack height and usable bandwidth per package area.
- Compute capability and flexibility: performance of the RISC-V design and how readily customers can customize it.
- Manufacturability: process compatibility, yield, thermal management, reliability and production scale on PSMC’s intended platforms.
None of these measurements is reported by the announcement, so they should not be inferred from the partners’ qualitative descriptions.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What happens next is still open
The announcement establishes a strategic direction rather than a delivery schedule. It does not say when an architecture will be frozen, when a prototype will be tested, which process node or packaging flow will be used, or when customers could access a foundry service. It also does not name an AI product or disclose validation results.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
For now, the concrete development is the agreement to combine CEA-List’s customizable RISC-V design capability, CEA-Leti’s silicon-photonics and microLED/GaN work, and PSMC’s 3D-stacking and interposer manufacturing platforms. Evidence of technical or commercial success will require subsequent specifications, measured results and customer or production announcements.
Quick Recap
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