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This project builds a custom bare-metal video pipeline on the AMD Kria KV260: programmable logic generates a test pattern, and the board sends it to a DisplayPort monitor through the processing system’s live-video path. The reference design uses a 4096 × 2160 raster and 100 MHz, 300 MHz, and 297 MHz clock domains. This first part focuses on the Vivado hardware design; the companion software flow initializes the video IP and DisplayPort interface from C firmware.
What the KV260 design does
The pipeline uses the Video Test Pattern Generator (TPG) in the programmable logic (PL) to create video without a camera or other external source. The stream passes through video timing and output IP, then reaches the KV260’s DisplayPort path. That path is exposed through the processing system (PS), so the design enables PS-PL Live Video mode to bridge the PL-generated stream to the PS DisplayPort interface.
The 2022 Hackster.io Part 1 tutorial by Nikil Thapa describes a bare-metal 4K TPG video pipeline. A 2026 refresh by Fredo Velasco describes the target as 4K at 30 Hz, with C firmware running on one Quadcore ARM Cortex-A53 core. The published material does not provide reproducible latency, power, sustained-throughput, or failure-rate measurements.
Check the hardware and tool setup first
Physical equipment
The refreshed guide lists these items for its setup:
#1 Best Overall
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
- AMD Kria KV260 Vision AI Starter Kit
- 12 V, 3 A, 60 Hz, 2.5 mm AC adapter
- USB-A to Micro-USB data cable
- DisplayPort cable and a 4K monitor
- Windows PC
- Anti-static mat and wrist strap
The guide says the board does not include peripherals or a power adapter, so confirm the adapter’s specifications and compatibility before powering the kit.
Choose a matched toolchain context
| Reference flow | Tools and operating system | What to keep in mind |
|---|---|---|
| Original tutorial | Vitis Unified Software Platform 2021.1; Ubuntu 20.04 LTS | The 2022 tutorial’s IP settings and software steps belong to this tool context. |
| Refreshed guide | Vivado/Vitis 2025.2; Windows 11 | The guide warns that project paths without spaces are important for its setup. |
These are separate tutorial contexts, not interchangeable step-by-step instructions. IP configuration screens, drivers, and APIs can differ by release, so use the documentation and generated platform outputs for the version you choose. AMD’s UG1089 revision 1.4, released June 25, 2025, documents KV260 Vitis base platforms; a listed platform supports 4K30 and 1080p30 NV12 video with DisplayPort/HDMI output. That prebuilt platform is not the same thing as the custom TPG design described here.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Build the hardware design in Vivado
Assemble the IP-integrator pipeline
The reference block design contains the Zynq UltraScale+ MPSoC Processing System, Video Test Pattern Generator, Clocking Wizard, Video Timing Controller (VTC), and AXI4-Stream to Video Out. Configure the PS for the KV260 target and enable PS-PL Live Video mode so video originating in the PL can use the PS-side DisplayPort interface.
The tutorial configures the TPG for 4096 × 2160 pixels. This is a 4096-wide raster, rather than the 3840 × 2160 UHD raster often also called “4K”; do not silently substitute one for the other when matching the timing and monitor mode. The refresh describes 4K at 30 Hz, but the cited material does not publish further timing or bandwidth measurements.
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Rank #3
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
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Respect the reference clock domains
| Clock domain | Reference frequency | Role in the tutorial |
|---|---|---|
| AXI-Lite | 100 MHz | Control interface for configuring video IP |
| AXI Stream | 300 MHz | Streaming video path |
| Video | 297 MHz | Video clock |
These are the original tutorial’s clock figures, not a universal recipe for every KV260 project or Vivado release. Preserve the intended clocking and interfaces when reproducing that design; if you change the raster, frame rate, or IP configuration, revalidate the clocking and timing together rather than carrying over a frequency by assumption.
Check color-channel ordering if colors look wrong
The original tutorial notes that a color-channel shift may occur and recommends inserting an AXI4-Stream Subset Converter with an appropriate TDATA remap when that symptom appears. Treat this as a troubleshooting option, not evidence that every board or build has the issue. Verify the stream’s channel ordering against the expected output before adding a remap.
Rank #4
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
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- Works with all operating systems: Windows, Mac, Linux
Export the platform and prepare the bare-metal application
Once the Vivado design is configured, export the hardware platform for Vitis. The refreshed guide describes exporting the hardware outputs as an .xsa and .bit, then importing them into a Vitis platform and a bare-metal application. Exact export and import labels may vary by tool version.
- In Vivado, complete the custom block design and generate the hardware outputs for the chosen KV260 target.
- Export the hardware platform, including the outputs required by the selected tutorial flow.
- In Vitis, create or import a platform from those hardware outputs, then create a bare-metal application for it.
- Use C firmware to initialize the PL-side TPG and VTC through their AXI-Lite interfaces.
- Initialize the KV260 DisplayPort interface in software as well; configuring the PL video IP alone does not complete the output path.
The Part 2 tutorial adapts Xilinx’s xdpdma_video_example_1 sources, including xdpdma_video_example.c, xdpdma_video_example.h, and xdppsu_interrupt.c, for that DisplayPort initialization. Match the example sources and APIs to the Vitis release used for the project.
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Keep the implementation path aligned with your goal
- Custom test pattern to DisplayPort: Use the custom PL design and PS-PL live-video route described here when you need a generated test pattern and control over the IP-integrator pipeline.
- Prebuilt platform: AMD’s documented KV260 base platforms are a different starting point. Check that the selected platform supports the required video format and output interface rather than assuming it reproduces this custom TPG design.
- Different output or input: This project targets DisplayPort and a generated pattern. An HDMI target, camera input, or codec pipeline changes the relevant hardware and software requirements; the cited tutorial does not establish those variants.
What to verify when the display stays blank or looks incorrect
- Confirm that the project targets the KV260 and that the PS configuration enables PS-PL Live Video mode.
- Check that the VTC, TPG, AXI4-Stream to Video Out, and clocking configuration agree on the intended raster and timing.
- Confirm the firmware initializes both the PL video IP and the DisplayPort path.
- If the image appears with shifted colors, inspect the stream channel ordering and consider the tutorial’s AXI4-Stream Subset Converter remap.
- For the refreshed Windows setup, keep the project path free of spaces as its guide advises.
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